In this paper the technoeconomical benefits in the use of Ensemble of Regression Trees (ERT) Machine Learning method are explored for fish shape alignment. Various ERT models are trained on low contrast blur images of open water Mediterranean fish species. Shape alignment can be used to estimate morphological features (length, weight) and species variety. Moreover, shape malformations and color analysis of fish parts located by certain shape landmarks can also be used to assess freshness or fish health. Shape alignment based on 26 landmarks has been performed with a relative mean average error (MAE) of less than 3% and fish length estimation with MAE$<2 \%$. Hardware acceleration with reconfigurable hardware can be applied in some of the trained ERT models to perform a single fish shape alignment in less than 15 ms.

The safe and secure implementation of increasingly complex features is a major challenge in the development of autonomous and distributed embedded systems. Automated design-time procedures that guarantee the fulfillment of critical system properties are a promising approach to tackle this challenge. In the European project XANDAR, which took place from 2021 to 2023, eight partners developed an X-by-Construction (XbC) design framework to support developers in the creation of embedded software systems with certain safety, security, and real-time properties. The design framework combines a model-based toolchain with a hypervisor-based runtime architecture. It targets modern high-performance hardware, facilitates the integration of machine learning applications, and employs a library of trusted safety and security patterns to reduce the implementation and verification effort. This paper describes the concepts developed during the project, the prototypical implementation of the design framework, and its application in both an automotive and an avionics use case.

The 2D facial landmark alignment method, implemented in C++ in the open source libraries DLIB and Deformable Shape Tracking (DEST), is used in several applications such as driver drowsiness detection. The most challenging of these applications require fast video frame processing. Therefore, the alignment of the facial landmarks in a single video frame has to be performed with the minimum possible latency without precision loss. In this paper, the DEST implementation of the face alignment method that is based on regression trees is heavily restructured to reduce latency. The resulting face alignment predictor is implemented in C. The elimination of multiple nested routine calls, excessive argument copying, type conversions and integrity checks lead to a software implementation that is 240 times faster than the one provided in the DEST library. Moreover, the structure of the new face alignment predictor is appropriate for hardware implementation on a Field Programmable Gate Array (FPGA) for further acceleration1.

In the context of this paper, a shape tracking application based on landmark alignment is transformed to support implementation in Field Programmable Gate Arrays (FPGAs). Towards this direction, several challenges are posed since a) computational intensive operations have to be replaced by faster ones, b) specific loops have to be modified (e.g., unrolled) to support the implementation of operations in parallel with different hardware resources, c) multiple pretrained models have to be compared in terms of speed and accuracy, d) partial loading of the pre-trained models has to be examined in order to fit their parameters in the Block Random Access Memories (BRAMs) of the FPGA for faster access, and e) alternative arithmetic representations have to be evaluated for higher speed and reduced resources.The C++ Deformable Shape Tracking (DEST) implementation of face alignment that is based on an Ensemble of Regression Trees is employed in our approach. The DEST application uses Eigen library routines to implement algebraic operations which are proved to be quite slow. The achievements of this paper, concern the replacement of appropriate Eigen calls in time critical paths with fast C code that can be directly used to synthesize reconfigurable hardware implementations. The elimination of the computational intensive Eigen calls has already improved the speed of the face alignment application by more than 240 times. In this paper we examine how the modified source code structure of the DEST application can be used to address the challenges described above.

An ultra low area 8-bit Analog-to-Digital Converter (ADC) has been designed achieving a 150 MS/S sampling rate and dissipating 34 mW power. It is based on integer division circuits that are arranged in a binary tree structure. We emphasize on the digital calibration method of such an ADC in order to extend its operational temperature range and correct the effect of mismatch and process variations. The calibration is achieved by controlling the voltage supply of the root divider and the amplification and offset correction of the residue that is produced by this divider.

A configurable asynchronous CMOS TSMC90 nm Analogue to Digital Converter (ADC) with 4, 8 or 12-bits resolution, using a binary tree structure is presented which needs very low silicon area and relatively low power consumption for its implementation. The sampling rate of the 12-bit ADC exceeds 140MS/s and requires only 0.12 mm2of area making it appropriate for ultra wideband time-interleaved parallel ADC architectures.

A system capable of estimating the position of a mobile target based on the error rate of the received infrared patterns has been presented recently in [1]. In the present work, we explore the effect of using different infrared patterns to the estimation accuracy, the instant noise immunity and the system speed. We apply interleaving and forward error correcting techniques to correct the burst errors stemming from instant noise. We achieved a 25%-50% stability improvement, retrieved 20% less failures and the convergence speed is enhanced by a factor of 4-12.

In this paper we present a way to locate the position of a moving target on a grid plane of about 15 square meters with an estimation error of less than half of the grid node distance. The estimation method is based on the success rate that the infrared patterns transmitted from two constant positions is received by the moving target. Several aspects of the reception such as the number of the expected, scrambled or out of order patterns that are recognised are considered. They are all playing an important role in determining the coordinates of the target. An ultra low cost system architecture based on commercial components is presented. A proper carrier filter of 1 MHz centre frequency is also studied in order to achieve fast coordinate estimation. The accuracy of the position estimation algorithm is also discussed with respect to the effect of the grid node distance.

An object oriented (OO) methodology that allows system-level prototyping of embedded applications is presented in this paper. Apart from the typical benefits of OO, i.e. correct capture of specifications, reusability of models and efficient management of design complexity, we also show how an OO system model can be used for guiding the partitioning of the application and for the exploration of alternative implementations. This is demonstrated through a real application from the image processing field.

The design and joint simulation of the heterogeneous parts of a system in a unified environment offers many advantages including reduced system design and debug times as well as increased simulation accuracy. This paper presents a couple of flexible interfaces that have been implemented for bridging VHDL with electromechanical systems simulators (EMSS) and VHDL simulators with the application programs that control the digital circuit simulated in VHDL correspondingly. These interfaces are based on the use of VHDL interface components with generic structure that simplify the whole simulation procedure. The basic concepts and features used for these implementations are characterized by increased portability while other significant advantages of the proposed schemes are their speed, their flexibility in supporting various communication protocols and the simplified and fully automated simulation procedure which is transparent to the user.