This letter introduces a new direction-of-arrival (DOA) estimation approach for mixed coherent and uncorrelated signals. The technique extracts cross-diagonal elements from the covariance matrix to form Toeplitz matrices, then averages them using a counting matrix to effectively decorrelate signals. This provides more accurate covariance estimates for subsequent subspace-based DOA estimation methods. Compared to existing approaches, the proposed method offers more degrees of freedom (DOFs) and lower computational complexity, while robustly detecting the directions of mixed coherent and uncorrelated signals under low signal-to-noise ratio (SNR) and limited snapshot conditions.

This paper presents a fully integrated W-band multi-channel silicon-based radiometer array in a 65-nm CMOS process. Four channels are integrated to achieve higher resolution and sensitivity. A single channel consists of low noise amplifier (LNA), detector, and analog baseband (ABB), respectively. The four-stage LNA achieves a power gain of 29.9dB, a minimum noise figure (NF) of 5.0dB over the band of interest. The detector achieves responsivity of 2.34 kV/W and 23.9$\mathbf{pW}/\sqrt{\text{Hz}}$noise equivalent power (NEP). The radiometer achieves a responsivity of 42293 MV/W, an NEP of 0.21$\mathbf{fW}/\sqrt{\text{Hz}}$, and a temperature resolution (NETD) of 0.226 K with a 1 ms integration time. The total power consumption is 254.6 mW.

This paper presents a high-precision and energy-efficiency Capacitively-coupled Chopper Instrumentation amplifier (CCIA) for Wheatstone bridges readout. The Ripple Reduction Loop (RRL) structure is improved to enhance the attenuation effect. In addition, a novel Noise-Nonlinearity-Cancelling Loop (NNCL) is introduced to alleviate the noise contribution come from RRL. The power consumption of this part of circuit is ultra-low, so the whole amplifier still has a competitive Noise Efficiency factor (NEF). Switch-capacitor circuits and duty-cycled resistors are used respectively to improve the PVT robust stability of the design, where large resistors are demanded. The circuit is fully integrated in a 65- nm CMOS technology with a 1.0 mA current from a 1.8 V supply voltage. The CCIA achieves an input-referred noise density of 2.8 nV/√Hz and a NEF of 3.38.

In this paper, we propose a fractional-N PLL with charge pump linearization circuit to mitigate quantization noise fold-in and reference spur deterioration issues simultaneously. This linearization circuit with a novel clock gating technique can suppress the fold-in quantization noise to -110 dBc/Hz, without degrading the reference spur or incurring additional digital algorithm, and the power consumption is negligible, while prior arts either cause large reference spur due to strong instantaneous current mismatch or consume too much power. A process robust cascaded spur trapper is also proposed to guarantee at least an extra 20 dB attenuation of reference spur.

In this paper, we present a novel deep neural network (DNN) dedicated to dynamic gesture control based on a radio-frequency (RF) type sensors. The proposed network is based on auto-encoder (AE) and long short-term memory recurrent neural network (LSTM-RNN). The encoder for reduction and effective feature extraction is obtained by unsupervised training an AE with a large untagged RF database. Further a light LSTM network is trained use a small size of tagged datasets for dynamic gesture classification. Training the network with semi-supervised learning methods greatly reduces the requirement on the size of the tagged gestures datasets. Experimental results demonstrate that our AE-LSTM method outperforms existing networks in terms of accuracy and realizability. The proposed application is used for the human-computer interaction (HCI) of intelligent home, automatic driving and robot scenes.

This paper presents a 20-Gb/s optical receiver consisting of a novel transimpedance amplifier (TIA), three active feedback Cherry-Hooper limiting amplifiers (LA) and DC offset cancellation loop. A novel cross-coupled dual-feedback loop TIA is proposed to reduce the input impedance and enhance the tolerance of large input capacitance without deterioration of the transimpedance gain. Moreover, not any extra noise, power consumption or chip area is introduced. Implemented in 65-nm CMOS technology, the receiver achieves 73.1 dBΩ transimpedance gain with a bandwidth of 10.2 GHz and a data rate of 20 Gb/s, while the input referred noise (IRN) current is below 30.5 pA/√Hz from 1 to 10.2 GHz. The core circuit consumes a DC power of 9.6 mW from a 1.2V supply (without output buffer) and occupies a layout area of 0.042 mm2.

This paper presents an accurate dB-linear programmable-gain amplifier with temperature-robust characteristic. A novel Gm-cell feedback topology is proposed to provide linear gain control as well as bandwidth extension without any extra power consumption. Moreover, a PTAT bias is employed to further promote the temperature robustness while AC coupling stages are embedded in the adjacent stages for DC-offset cancellation. Implemented in TSMC 65-nm CMOS technology, the proposed PGA exhibits a programmable gain range of 0 dB to 42 dB with 1 dB per step and 0.17 dB error. The gain variation across -40~125 °C is lower than 0.3 dB at all gain settings. The core circuit consumes a DC power of 3.8mV from a 1.2 V supply and occupies a layout area of 0.048 mm2.

This paper presents an automatic amplitude control (AAC) loop voltage controlled oscillator (VCO) with a constant VCO gain (Kvco) for fractional-N frequency synthesizers in WLAN application in 65nm CMOS process. A novel AAC scheme based on a mixed-signal feedback loop has been proposed to minimize the amplitude variation. In order to achieve a low Kvco variation, an extra switched varactor array is also introduced to the LC tank together with the conventional switched capacitor array. The VCO achieves a tuning range of 23.7% from 3.1 to 4.2GHz, while consuming 4.6mA of quiescent current from a 1.2V power supply. The peak amplitude variation over the entire frequency range is less than 10mV, which can be otherwise as large as 100mV, or 22.2% without the AAC loop. The VCO shows a nearly constant Kvco of 60MHz/V, a low phase noise of -123.3dBc/Hz at 1 MHz offset, and a superior FoM of -187dBc/Hz from a 3.6 GHz carrier.

In this paper, a fully integrated 24GHz integer-N PLL for a 60GHz wireless transceiver is presented. A VCO with tail-feedback technique is used to improve the phase noise by modulating the tail current, and a switched varactor array is also adopted together with a switched capacitor array to compensate the variation of KVCOover different bands. Moreover, benefiting from the careful optimization of CML pre-scaling divider, the PLL operates correctly when VCO buffer is turned off, coming up with an extremely low power. The whole PLL is fabricated in standard 90-nm process. Measurement shows that the VCO achieves a phase noise of -102dBc/Hz@1MHz offset with a tuning range of over 16%. The KVCOvariation over all bands is less than 16%. In close-loop operation mode the PLL shows an integrated phase error of 3.3°rms (from 100kHz to 100MHz) over prescribed frequency bands, and a total power dissipation of only 26mW.

A 60GHz receiver for 802.11ad application with superior performance in 90nm CMOS process, compared with prior arts in advanced processes, is proposed and realized. A 3-stage differential LNA achieves a gain of 19.8dB and a noise figure of 6dB in measurement, showing less than 0.3dB difference from simulation due to the elaborate consideration of parasitics. A baseband PGA with wideband and large gain tuning range is achieved from modified Cherry-Hooper amplifier with negative capacitive neutralization technique. The entire receiver achieves a double-side-band NF of 7.1dB and a maximal conversion gain of 64dB with 28dB tuning range, while consuming only 177mW of power. The measured output P1dBis -5.5dBm. All measured results are rigorously loyal to the simulation.

In this paper, a wide-band inductor-less LNA for low voltage operation is presented. The input matching is implemented by using a feedback transistor with a resistor terminated to the source to enhance linearity and to reduce noise. Current reuse technique is employed to increase the total transconductance. Under 1V supply voltage and a DC of 5.6 mA, the LNA achieves an average noise figure of 3.2 dB, a maximum voltage gain of 18.6 dB, and 3 dB bandwidth ranges from 0.2-4.5 GHz.

Phase noise of oscillators can be improved through noise filtering. This paper presents a transformer-based harmonic filtering technique to improve the phase noise performance of the fully differential CMOS LC oscillators. The primary and secondary of the transformer are placed at the sources of NMOS and PMOS differential pairs, respectively. Due to the extra degree of freedom introduced by the transformer, the filter can resonate at two different frequencies, which are designed to be the second and fourth harmonics. The analysis of the filtering method is presented and principles of operation are discussed in details. The performance is compared with other filtering techniques, and the simulation results show improved FoM compared to published literature.

An analytical framework has been developed to describe the locking behavior of millimeter (mm) wave current mode logic (CML) frequency divider. Unlike traditional analysis based on RC delay, the proposed model is established with injection-locking concept from analog perspective. Both analytical formulas and graphic interpretation are provided for design insights. The model has been validated by exhaustive simulations and important guidelines have been concluded for circuit design.