Image and signal processing workloads are widely deployed on Graphics Processing Units (GPUs) for high throughput and on Field-Programmable Gate Arrays (FPGAs) for hardware specialization and energy efficiency. Soft GPU overlays on FPGAs aim to combine these advantages, yet existing solutions often depend on fixed hard processors or impose platform constraints that limit portability. This work extends a popular open-source soft GPGPU overlay to integrate a soft RISC-V control plane and enable compatibility with High-Bandwidth Memory (HBM2). The resulting system can be instantiated on FPGA boards without a hard ARM processor, improving portability, simplifying system integration, and broadening deployability. Across representative image and signal processing kernels, the soft GPGPU achieves geometric-mean speedups of 114.60 × over a scalar soft RISC-V core and 19.72 × over a hard ARM core, demonstrating substantial performance benefits while retaining FPGA reconfigurability. HBM2 integration further benefits bandwidth-sensitive workloads by increasing sustained throughput and reducing the performance bottlenecks associated with off-chip memory access. Collectively, these results indicate that GPU-like programmability and performance can be delivered on reconfigurable platforms without reliance on hard CPU subsystems, providing a portable and scalable foundation for embedded vision and DSP acceleration.

Machine learning algorithms are becoming more complicated with time in order to solve complex problems. This is creating a gap for embedded system solutions e.g. General-Purpose Processors (GPPs), Graphic Processing Units (GPUs), and hardware accelerators, for the machine learning algorithms. To bridge the gap between the available solutions, Application Specific Instruction-set Processors (ASIPs) are a promising solution. ASIPs are processor designs with a tailored architecture for a specific application. This allows a better efficiency (performance-to-power) ratio for the application ex-ecution. Furthermore, it adds more flexibility to the system as compared with hardware accelerators. The scope of this Ph. D. work is to develop a RISC-V-based ASIP for machine learning applications and explore the design space of the optimizations. RISC-V is an open-source Instruction-Set-Architecture (ISA) and allows the addition of custom application-specific instructions to the ISA. In the scope of this work three main design space optimization of ASIPs will be explored; specialized application-specific ISA, vector processing (for data-level parallelism), and multi-core architecture (for task-level parallelism). RISC- V 32-bit architecture is used as the base platform. For vector processing, RISC- V V-extension is utilized for a SIMD-based architecture called Vector Processing Unit (VPU) which is coupled with a 32-bit RISC- V host CPU. A modular memory system is implemented to have a shared (bus-based) and distributed (NoC- based) multi-core system. The memory system increases the flexibility and scalability of the system. Other known machine learning platforms are also explored and used as a comparison case.

The computational intensity in embedded processing applications is increasing. This requires domain-specific embedded platforms in order to achieve maximum performance per watt of the system. With the arrival of open-source instruction set architectures such as RISC-V, and different domain-specific architecture development toolchains, the trend of application-specific architectures is increasing. In this paper, a parameterizable Vector Processing Unit (VPU) is presented based on a subset of V-extension from the RISC-V instruction set architecture (ISA) for embedded processing. Two key configurable parameters for the proposed VPU are vector length (VLEN) and the number of execution lanes. These parameters allow design space exploration for the VPU for different configurations and help to understand which application scenarios would fit for certain configurations. The proposed VPU was integrated into a 32-bit RISC-V processor. For maximum parallelization configuration, 2.3 x fewer cycles per instructions were achieved as compared to a RISC-V processor. Moreover, a relative cycle gain of 33-73% was achieved for different configurations as compared with the RISC-V processor.

A major concern with battery-operated devices is power-awareness and its appropriate computing. The power dissipation of such systems is usually considered a hardware problem. However, it can be solved by implementing power-aware techniques. Such algorithms have shown promise as an approach to dynamically adjust the power consumption of embedded systems within feasible ranges. One of the most popular power-saving techniques is Dynamic Voltage and Frequency Scaling (DVFS). Besides the power management, an accurate and fast power monitoring service is necessary on embedded platforms to reduce power consumption. In this paper, we provide an overview of power-aware computing platforms based on different application domains. It intends to summarize recently published research results related to power-aware computing architectures using Field Programmable Gate Arrays (FPGAs). We identify trends and highlight key future directions for power management techniques and power monitoring services.

Motivated by an increasing interest from startups in embedded Artificial Intelligence (AI) and by their limited expertise, the AITIA Project targets the development of embedded AI techniques for industrial applications. This extended abstract presents the motivation and the solutions being developed towards four use cases: smart sensors, network intrusion detection, driver-assistance systems, and Industry 4.0.