Defect maps of 57 wafers containing large area VLSI IC's were analyzed in order to find a good match between the empirical distribution of defects and a theoretical model. Our main result is that the commonly employed models, most notably, the large area clustering negative binomial distribution, do not provide a sufficiently good match for these large area IC's. Only the recently proposed medium size clustering model is close enough to the empirical distribution. An even better match can be obtained either by combining two theoretical distributions or by a "censoring" procedure in which the worst chips are ignored. Another goal of the study was to find out whether certain portions of either the chip or the wafer had more defects than the others.>

It has been recognized that the yield of fault-tolerant VLSI circuits depends on the size of the fault clusters. Consequently, models for yield analysis have been proposed for large-area clustering and small-area clustering, based on the two-parameter negative-binomial distribution. The addition of a new parameter, the block size, to the two existing parameters of the fault distribution is proposed. This parameter allows the unification of the existing models and, at the same time, adds a whole range of medium-size clustering models. Thus, the flexibility in choosing the appropriate yield model is increased. Methods for estimating the newly defined block size are presented and the approach is validated through simulation and empirical data.>

Several improvements in the method of yield modeling for memory chips with redundancy are described. First, a direct method of translating defect-monitor data to memory-chip fault eliminates the need for yield-model formulas. This makes possible the accurate modeling of the faults that can be fixed with redundant circuits or other fault-tolerance techniques. A second improvement results from the use of separate frequency distributions for different failure mechanisms instead of the multivariate distributions used until now. The yields of array islands with their own redundant word and bit lines are combined using a new yield formula. Examples of the use of this technique for dynamic-random-access-memory (DRAM) chips are given. A simplified pragmatic approximation technique that appears to be in good agreement with experimental data is also discussed.>

The discovery of a principle of synergistic fault tolerance is described, and it is shown analytically why it occurs. The performance of its hardware implementation, in the form of a VLSI memory chip, is reported. An analysis of the error-correction scheme implemented in the hardware is presented, and limitations to the use of error-correcting codes for fault tolerance are explained. Methods for circumventing these limitations with the use of redundant circuits are discussed, analyzing the effect of bitline and wordline redundancy. The result of the analysis shows how the combination of error-correcting codes with redundant circuitry results in a fault-tolerance synergism.>

Clustered faults that affect the manufacture of integrated circuits are modeled by a simulation approach in which the fault formation is a function of time. In one such approach, the probability of generating a fault in a given subarea of an integrated circuit at any given time is assumed to depend on the number of faults already in that area and on the number of faults in the nearest-neighbor adjacent subareas. Although such procedures had been used heuristically, technical considerations show that this stochastic approach actually is analytically justifiable. It is found that the resulting distribution functions, the joint probability distribution function, the distribution function of the sum of dependent random variables, and the correlation between these variables are identical to results obtained with a large-area cluster model using compound Poisson statistics. This offers a unique insight into a statistical isomorphism that has been a puzzling issue.>

Two methods used in fault simulation for integrated circuit modeling are described. Both methods simulate clustered fault locations on a map. In the first approach, the clusters are initially generated using a radial Gaussian probability distribution. The results are consequently passed through cluster shaping programs, which produce clusters that resemble those observed on actual integrated circuit wafers. In the second approach, faults are added to the chips as a function of time. The probability that additional faults are created during any interval of time is assumed to be related to the number of faults already on the chip, as well as the number of faults on adjacent chips. This technique generates frequency distributions of the number of faults per chip that closely resemble those observed in actual integrated circuits.>

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