This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests for stuck-at faults. The proposed method is suitable for use in testing scan designs that employ enhanced scan. The method reduces the peak power consumption in benchmark circuits by 19% on the average with essentially the same test set size and the same fault coverage compared to an earlier method.

Recently, Markov sources were shown to be effective in designing pseudo-random test pattern generators with low area overhead for built-in self-test of scan designs. This paper presents a new test pattern generation scheme based on a Markov source and a partial bit-fixing technique. A new method is proposed for the computation of the state transition probabilities of the Markov source based on the statistics of a deterministic test set. This is enhanced by partial bit-fixing logic, which fixes a group of consecutive inputs to all-0 or all-1. Experimental results show that the proposed BIST scheme can achieve 100% fault coverage for large benchmark circuits with reduced hardware overhead and reduced pattern counts compared to the earlier method using Markov sources.

Recently, Markov sources were shown to achieve 100% fault efficiency at low area overhead when used as pseudo-random pattern generators in scan BIST. In this paper we give a new method of designing Markov sources. The new design attempts to match probabilities of 1 to 0 and 0 to 1 transitions in consecutive bits of a set of test vectors, taking into account that the transition probabilities may be different for different bit positions. Experimental results show that the proposed method considerably reduces the hardware overhead and test lengths required to achieve 100% fault coverage.