Solid state drives (SSDs) based on NAND flash technology are steadily gaining popularity and mass market adoption due to their increased storage capacity and density. However, because of the more bits in each cell and the reduced cell spacing, they are experiencing a decline in reliability. The most efficient way to ensure reliability of data is to use low-density parity-check (LDPC) codes. Nevertheless, using a hybrid decoding technique for LDPC codes results in a significant decoding latency, which exacerbates performance issues. In this paper, we propose a variable-dimensional LDPC coding scheme, called VDLDPC, to reduce the high decoding latency and thus improve read performance of NAND flash memory on hot read data. One of the crucial designs in the VDLDPC scheme is the two-dimensional LDPC (TD-LDPC) algorithm. TD-LDPC implements row and column encoding separately when writing data to the flash memory by using sub-LDPC codes. Errors in the data arise after a period of retention. When the data is read out, TD-LDPC performs row and column decoding using sub-LDPC codes, and the column decoding result can be re-decoded as a new round of row decoding input. Simulation results show that the proposed VDLDPC scheme has the advantage in decoding latency and reduces the flash memory read response time by up to 12.0% (5.8% on average across all workloads) compared to the current LDPC code scheme. The proposed VDLDPC scheme ensures reliability while improving NAND flash system read performance on hot read data.

Through stacking and multi-bit technology, three-dimensional (3D) flash memory enhances storage capacity and density; nevertheless, the reduction in noise margin results in an increase in raw bit error rate (RBER) and a decrease in data reliability. Low-density parity-check (LDPC) codes are widely used in flash memory for improving data reliability because of its strong error correction capability. In the early stages of 3D flash memory use, the RBER is low, and hard decision decoding (e.g., bit flipping decoding) is generally invoked for error correction. Existing LDPC codes with dynamic threshold bit flipping (DTBF) decoding algorithms cannot correct bit errors when the gradually increasing RBER exceeds its error correction threshold, resulting in an increase in decoding latency. To enhance error correction capability and reduce decoding latency, this paper proposes SiDTBF: merging soft information with DTBF LDPC decoding for 3D NAND flash memory. First, the read reference voltage of various interval lengths is applied in accordance with the threshold voltage distribution drift characteristics of the 3D flash memory cell to get the decoding soft information of each bit. Second, the strong and weak bits are distinguished using the soft information. In contrast to weak bits, which are more likely to be erroneous, strong bits are more likely to be correct. Finally, all the strong and weak bits are input as initial values for bit-flip iterative decoding. Using the column weight of the parity-check matrix, the threshold for the number of flipped weak bits is determined in the first decoding iteration process. The portion of the weak bits that exceeds the threshold is flipped. In the ensuing iteration phase, the DTBF decoding algorithm is used. SiDTBF improves decoding error correction performance by fusing each bit’s soft information with the DTBF algorithm during the decoding phase. Simulation results show that compared with current DTBF, SiDTBF significantly improves bit flipping decoding error correction capability and reduces decoding latency.

Dynamic random access memory (DRAM) is being upgraded iteratively, and as a result, its transmission rate and bandwidth are rising quickly. Simultaneously, as the DRAM process has advanced, the storage cell size has decreased and cell integration has improved within each device, leading to a significant boost in storage capacity and density. DRAM has been widely utilized as a crucial storage component in personal computers, mobile devices, servers, and data centers because of these benefits. However, data reliability is greatly hampered by DRAM’s vulnerability to single-bit, row, and column errors, which result in data loss and corruption as well as the possibility of system crashes and downtime. Error correction codes (ECC) are used by DRAM to protect data and increase reliability, but because large capacity DRAM is more prone to multi-bit errors of cross-chip. Traditional error correction strategies are unable to keep up with the demand for multi-bit errors of cross-chip. Therefore, a crucial problem that needs to be solved is the design of an ECC strategy with robust error correction capabilities. A high order ECC scheme with stronger error correcting capability is developed at a higher firmware layer without changing the hardware architecture to address reliability issues brought by DRAM multi-bit errors of cross-chip. The higher order ECC technique is then used to gain a stronger error correction capability while minimizing the latency overhead when an uncorrectable error is discovered by rank-level ECC (RECC). The error correction performance of the proposed high order ECC algorithm is evaluated and verified using simulation experiments in terms of both error correction capability and encoding/decoding latency. Simulation results show that compared with existing ECC schemes, the proposed high order ECC scheme for DRAM reduces latency by 69% and storage overhead by 5.56%. The proposed high order ECC method has significant research implications and is useful in preventing data loss and enhancing DRAM reliability.