A wideband full-duplex (FD) receiver with enhanced-linearity technique and shared self-interference cancellation (SIC) is implemented in a 40-nm CMOS process. By combining Hilbert-transform-equalization (HTE)-based self-interference (SI) canceller and translational loop, an FD receiver with RF domain cancellation is presented with an extra auxiliary cancellation path by reusing the mixer in the translational loop. By introducing the auxiliary path, the influence of SI circuit to receiver front end is minimized. Meanwhile, a self-loaded linearization technique with acceptable noise degradation and extra power consumption is proposed to be employed in the FD receiver for both receiver and SI canceller. Due to the 2-D regulation, such a technique can achieve a relatively robust linearity improvement and bring flexibility to circuit design. The measurement results show that the proposed FD receiver operates across 0.8–3.5 GHz with a gain of 29.0–31.8 dB and a noise figure of 3.68–5.23 dB. The proposed linearization technique achieves 3.2–4.7-dB linearity improvement for receiver with only 0.45–0.64-dB NF degradation. In addition, the canceller with the proposed linearization method achieves RF domain delays ranging from 1.59 to 4.03 ns while demonstrating more than 6.33-dB linearity improvement. With the implementation of self-loaded technique and shared SIC, a greater than 23.4-dB RF domain SI suppression is measured across 40-MHz bandwidth (BW) with 64-QAM modulated signals in a circulator-based setup for the SIC scheme in this work with RX noise degradation of less than 1.38 dB.

This article comprehensively analyzes the effects of differential capacitor array mismatches on the decision levels of charge-redistribution-based successive-approximation-register (SAR) analog-to-digital converters (ADCs), reveals the intrinsic relation between the differential CDAC mismatches and the output code distribution of SAR, and proposes a bit-weight calibration (BWC) algorithm for SAR in terms of raw output codes, which does not require any modification to the original design. The proposed BWC is applicable to other architectures that incorporate a SAR as a substage, such as a pipelined SAR (P-SAR). Physical measurement results are presented for a pure SAR and simulation results are presented for a two-stage P-SAR, both of which verified the theoretical analyses and the proposed calibration method.

This paper presents a resistance self-biased inverse class-F23voltage-controlled oscillator (VCO). The VCO keeps ultra-low amplitude and phase mismatches by inducing a resistance between primary and secondary coils of the transformer. It also induces both 2ndand 3rdharmonic resonances to reduce 1/f3corner frequency. The VCO is designed in 40nm CMOS with frequency range of 12.1GHz to 16.5GHz. The post simulation results show that it achieves − 118dBc/Hz and −109dBc/Hz at 1MHz offset frequency at 12.1GHz and 16.5GHz respectively, whose 1/f3corner frequency is 54kHz and 20kHz. The power consumption of the VCO is 14.3mW at 1.1V supply. The core area is 0.03mm2.

In this article, a 0.7–2.5-GHz tri-mode reconfigurable receiver (RX) for global navigation satellite system (GNSS)/narrow band-Internet of Things (NB-IoT)/Bluetooth low energy (BLE) applications is realized targeting one chip capability of integrating both wide area network (WAN) and local area network (LAN) protocols as well as positioning characteristics in 28-nm CMOS process with a compact core area of 1.7 mm2. By applying the proposed variable gain wideband active balun-low noise amplifier (LNA), the RX achieves minimum noise figure (NF) of 2.8 dB with the power consumption of 43 mW. The harmonic rejection (HR) method suppresses the signal interference caused by ON-chip coupling. 68-dB 3rd HR ratio (HR3) is achieved with only one-stage HR circuit. The mismatch between$I$channel and$Q$channel may limit the image rejection of the complex bandpass filter (CBPF). Detailed mathematical analysis of the$I/Q$calibration circuit is provided. Owing to the virtual short characteristic of the amplifier, the$I/Q$calibration scheme achieves a high-precision phase calibration. About 60-dB image rejection ratio (IMRR) is obtained after calibration.

This paper presents a 0.5-3GHz full-duplex (FD) self-interference (SI) canceling receiver based on a unique Cartesian canceller which scales the phase and amplitude of TX replica to generate a cancellation signal with the same amplitude but opposite phase to SI leakage, and injects this reconstructed signal to the receiver (RX) input for subtracting the SI leakage in RF domain. A prototype FD receiver (FD-RX) is implemented in CMOS 65nm technology. The RX has an IB-IIP3 of -5dBm at 2MHz offset, and OOB-IIP3 of 25dBm at 60MHz offset from 2GHz carrier. In FD mode, TX and RX are operating simultaneously at the same frequency band, more than 27dB self-interference-cancellation (SIC) is achieved in single RF domain, and the effective IB-IIP3 is improved from -5dBm to 5dBm with less than 1.2dB noise degradation. The noise figure (NF) is better than 7.8dB in FD mode. The area of proposed canceller is only 0.07mm2, and the core area of FD-RX is 0.45mm2. The power consumption of entire FD-RX including canceller is 25-54mW from 1.2V power supply.

The automatic frequency calibration (AFC) technique is routinely used in the wideband frequency synthesizers which contain multiple voltage-controlled oscillator (VCO) tuning curves. In this paper, a counter-based AFC design method is presented. The relationship between the AFC counting time and the VCO tuning curve characteristic is quantitatively analyzed. An AFC circuit which uses a time-to-digital converter (TDC) in the counting process is developed. Simulation results show that the proposed circuit significantly reduces the AFC calibration time while preserving the calibration accuracy. The simulated error-free AFC time of the proposed AFC is less than 3 µs.

A CMOS 80-400 MHz 5THorder Chebyshev Gm-C low-pass filter with a unique auto tuning system is presented. The filter was designed and fabricated with TSMC 0.13-μm RF CMOS process. Experimental results show that the cut-off frequency of the filter can be tuned between 80-400 MHz, with a tuning step less than 7MHz and an average tuning error of 3.6%. The filter also realizes gain of 0-30 dB, IIP3 of 16.5 dBm and NF of 14-18 dB. Dynamic range of the filter for THD less than 1% is 74 dB. Power dissipation is only 9 mW with 1.2 V supply voltage.

A harmonic-suppressed regenerative divide-by-5 frequency divider is proposed. Incorporating the proposed quadrature-input regenerative divide-by-2 divider (QIRD), the divide-by-5 divider suppresses the output harmonic effectively. The divide-by-5 divider improves the quadrarture phase accuracy at the output. Compared with conventional dividers, the divider achieves an output I/Q phase sequence that is tracked with the input I/Q phase sequence. The design is fabricated in TSMC 0.13-um CMOS and operated at 1.2 V. While locked at 8.6 GHz, the divide-by-5 divider achieves a minimum unwanted sideband rejection of -38 dBc.

A low power sigma-delta fractional-N frequency synthesizer for software-defined radio (SDR) implemented in a 0.13 μm CMOS process is presented, based on a dual-mode VCO (DMVCO) reconfigurable between wideband mode and quadrature mode, with optimized automatic frequency calibration (AFC). The proposed optimized AFC enables a more accurate band selection as well as a lower power for a dual-VCO PLL. A multi-phase counter (MPC) accelerates the calibration process without ruining the calibration accuracy. Simulated phase noise is -123 dBc/Hz at 1 MHz offset from a 1.8 GHz carrier. The spectral purity is better than 45 dBc from the output of mixer. The locking time of PLL is about 40 μs with an AFC time less than lOμs. The 0.4-6 GHz synthesizer consumes only 35 mW to 51 mW from a 1.2 V supply.

This paper presents the design of a sideband-suppressed synthesizer for dual-carrier MB-OFDM transceivers covering 11 frequency bands from 6.2GHz to 9.4GHz and 3 frequency bands from 4.2GHz to 4.8GHz, each with a bandwidth of 264MHz. Careful band plan is made to minimize the complexity. The synthesizer generates 14 carrier frequencies from a single frequency source. Improvements are made to the circuits to further suppress the sidebands. The synthesizer chip is designed with TSMC's 0.13-μm RF CMOS technology. The circuit draws a current of 42mA from a 1.2V supply. It achieves a sideband rejection of 45dBc and a phase noise of -105dBc/Hz@1MHz.

This paper presents a current-mode 6~9GHz RF transmitter for OFDM-UWB system applications. By a current-mode low pass filter with variable gain between the digital-to-analog converter and the up-conversion mixer, this transmitter exceeds the traditional voltage-mode counterpart in terms of high linearity (+3.5-dBm output 1-dB compression point, +12.5-dBm output third intercept point) and low spurious emission (50-dB sideband rejection) with low power consumption (40-mA current under 1.2-V supply voltage). By an output power flattening technique, the output power ripple is restricted within ±0.5dB. By an inductor-less divider and active-inductor LO buffer, a small die area of 0.72 mm2is obtained with TSMC's 0.13-μm 1P8M RF CMOS technology. The design is verified through post-layout simulations.

This paper presents a Sigma-Delta fractional-N frequency synthesizer for multi-standard receiver. The synthesizer's output range is 1.8~5.8GHz and covers the standards of DCS1800, WCDMA, TD-SCDMA, WLAN802. Ha/b/g and Bluetooth. Frequency planning is elaborately done to make sure the synthesizer meets specifications of standards mentioned above. QVCO with a proposed phase shifter is shown to have better phase noise performance and more stable oscillation. Simulated phase noise is -119dBc/Hz at 1-MHz offset from a 4.2GHz carrier. Its FOM ranges from 181 to 187. The frequency synthesizer is fabricated in TSMC 0.13um CMOS process. Average power consumption is 55.92mW.

This paper presents a power-optimized quadrature VCO with wide-tuning range for UWB Receivers. The optimization of power is achieved by both optimum selection of LC tand and the improvement of the conventional VCO. To increase the tuning range, the digital controlled capacitor array is exploited. The circuitry is implemented by the 0.18um RF/mixed signal process. The proposed VCO achieves phase noise of 125dBc/Hz at 1-MHz offset and 34% tuning range while consuming 3.5mA in 1.6-V supply. Figure-of-merit with tuning range of the proposed VCO is which is the lowest among the recent state-of-the-art low-voltage VCOs.

A 1.9-GHz down-conversion CMOS mixer, intended for the GSM1900 (PCS1900) low-IF receivers is present with the utilization of novel folded Gilbert cell fabricated in an RF 0.18-/spl mu/m CMOS process. The prototype demonstrates a good performance. It achieves a conversion gain of 6dB, SSB noise figure of 18.5dB and IIP3 11.5dBm while consuming 7mA current from 3.3V power supply.