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Kuchibhotla V. Sastry

dblp:64/6051 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1975
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 54% Memory systems · 46%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory architecture
interleaved memory		 0.011975
On the Performance of Certain Multiprocessor Computer Organizations · IEEE Trans. Computers 1975
Performance modeling and evaluation › markov models
markov chain performance analysis		 0.011975
On the Performance of Certain Multiprocessor Computer Organizations · IEEE Trans. Computers 1975
Memory systems
memory interference		 0.011975
On the Performance of Certain Multiprocessor Computer Organizations · IEEE Trans. Computers 1975
Performance modeling and evaluation
queueing models		 0.011975
On the Performance of Certain Multiprocessor Computer Organizations · IEEE Trans. Computers 1975
Performance modeling and evaluation › parallel system performance
multiprocessor performance		 0.011975
On the Performance of Certain Multiprocessor Computer Organizations · IEEE Trans. Computers 1975

Methods — techniques the papers use, named apart from their topics

markov chain · 0.0analytic modeling · 0.0
YearPublicationVenuePosition
1975 On the Performance of Certain Multiprocessor Computer Organizations
abstract
Analytic models are developed to evaluate the performance of a multiprocessor computer system. Markov chain techniques are used to model memory conflicts when the memory is modularized. The instruction execution rate (IER) is chosen as the measure of performance. The performance is studied with different storage allocations for instructions and data and with interleaving in the instruction space.
Kuchibhotla V. Sastry, Richard Y. Kain
 IEEE Trans. Computers1