Signature monitoring has proven to be an effective method for concurrent detection of control-flow errors in processors. A recent proposal adapts signature monitoring to the concurrent checking of dedicated controllers or state machines. The authors extend this approach and present theoretical results, including existence-of-solution guarantees, as well as new, efficient synthesis algorithms. The algorithms have been implemented and successfully applied to a variety of machines including all of the machines in the MCNC benchmark set. For most examples, the evaluation and synthesis algorithms exhibit negligible running times and the resulting optimized machines exhibit reasonable overheads. There is strong indication that the efficient synthesis of self-monitoring, and possibly self-testing, state machines is feasible using this approach.>

It is shown how the substitution of a partial order facilitates automatic modeling in switch-level simulators that use the traditional total ordering of strengths for resolving conflicts between opposing signals while increasing the accuracy of that model. Minimization techniques are described that reduce the number of required modeling strengths to acceptable levels. As a result, the use of partially ordered strengths does not significantly degrade simulation performance. It is also shown how to rearrange the computations performed during switch-level simulation to yield a nearly twofold increase in speed for good circuit simulation. A switch-level simulator using this algorithm with partially ordered strengths has been successfully used to verify several full-custom industrial designs.>

A key idea in switch-level simulation is the use of a total ordering of signal strengths to resolve conflicts between opposing signals. For many circuits, however, it is not possible to assign such strengths to circuit elements in a logically consistent fashion without user intervention. It is shown that the use of a partial ordering of strengths avoids these difficulties and allows modeling to be done automatically. The authors also discuss the need to minimize the number of distinct strengths needed to model a circuit, because simulation times are affected by the number of strengths being used. This is especially important for compiled switch-level simulators that generate representations whose size is proportional to the number of strengths. Statistics on the application of these ideas to industrial chips are presented.>