As the number of frequency domains aggressively grows in today's systems-on-chip (SoCs), the delivery of high-delay test quality across numerous frequency domains while meeting test budgets assumes crucial importance. This paper proposes a method to explore the delay test quality tradeoffs across these domains, determining an optimal distribution of the test time budget across all domains while minimizing the overall SoC delay defect escape level. Satisfaction of this goal necessitates not only consideration of fault coverage but also of the distinct characteristics of each domain, such as frequency, path length distribution, scan length, and shift speed as well as full utilization of concurrent test support while remaining within the constraints of power thresholds to provide a reliable test environment. An optimization formulation as well as efficient test time allocation methods based on convexity and fast concurrent test planning algorithms are provided.

The inclusion of various new test types in production test suites with the hope of keeping defect escape level in check continuously increases the test cost while the economics of the intensely competitive consumer marketplace dictates test strategies that are low cost yet still effective in defect detection. An adaptive test methodology is proposed in this paper to address the simultaneous demand for efficiency and effectiveness in testing through an adaptive prioritization of test vectors according to defect detection effectiveness, subsequently, leading to the identification of a compact yet effective test set. Experimental results confirm the effectiveness of the vector prioritization process and show substantial cost reduction levels.

The increasing magnitude of process variations individualizes effectively each chip, necessitating distinct quantities of test resources for each in order to optimize overall delay test quality without exceeding set test budgets. This paper proposes an analytical framework that delivers the optimal test time assignment per chip in order to minimize the delay defect escape rate. Adjustment of the chip-specific test time in the continuous process variation space is attained through an adaptive test flow that utilizes process data measurements from the device under test. The results evince that a substantial improvement in the delay test quality can be obtained at no increase whatsoever to test time consumed by conventional test flows.

The increasing multiplicity of defect types forces the inclusion of tests from a variety of fault models. The quest for test quality is checkmated though by the considerable and frequently unnecessary cost of the large number of tests, driven by the lack of a clear correspondence between defects and fault models. While the static derivation of the appropriate test mixes from a variety of fault models to deliver high test quality at low cost is a desirable goal, it is challenged by the frequent changes in defect characteristics. The consequent necessity for adaptivity is addressed in this paper through a test framework that utilizes the continuous stream of failing test data during production testing to track the varying test quality based on evolving defect characteristics and thus dynamically adjust the production test set to deliver a target defect escape level at minimal test cost.

As the number of frequency domains aggressively grows in today's SOCs, the delivery of high delay test quality across numerous frequency domains while meeting test budgets is crucial. This goal necessitates not only the consideration of fault coverage but also the distinct characteristics of each domain such as frequency and the distribution of path lengths and, additionally, the delay test quality tradeoffs across these domains. This paper proposes a method to identify the optimal test time allocation per domain based on the distinct characteristics of each in order to minimize overall delay defect escape level. The proposed method not only considers test time allocation but also concurrent scheduling of domains to optimize the delay test quality for SOCs that support the testing of multiple frequency domains in parallel.

Defect characteristics and consequently test quality vary throughout the production life cycle. An optimal test methodology needs to adjust the test set based on the ever changing defect characteristics to deliver consistent test quality levels. In this paper, we propose an adaptive test framework that alters the test set continuously by utilizing the history of recent failures to track the instantaneous defect escape level, thus reaching the target test quality level at minimal test cost.

Production test suites include a large number of redundant test patterns due to the inclusion of multiple test types with overlapping defect detection and the use of simple fault models for test generation. Identification and elimination of ineffective test patterns promises a significant reduction in test cost. This paper proposes a test framework that learns, without extensive data collection and at no additional test time, the effectiveness of individual test patterns during production testing by getting defect detection feedback from a dynamic test flow. The proposed technique is further capable of adapting to changes in the underlying defect mechanisms by tracking the defect detection trend of test patterns.

The quality of a delay test set hinges not only on test patterns and the distribution of the delay defects but on the variations in process parameters as well. Process variations result in the same delay test set displaying differences from die to die in the detection of particular delay defects at the identical circuit node. The application of an identical test set to all devices independent of process variations consequently results in delivering inefficiencies in test time utilization. This paper proposes a delay test technique that adaptively changes the size of the test set based on the position of the device in the process variation space in order to maximize test quality within a given test time.

Scan-based designs are widely used to decrease the complexity of the test generation process; nonetheless, they increase test time and volume. A new scan architecture is proposed to reduce test time and volume while retaining the original scan input count. The proposed architecture allows the use of the captured response as a template for the next pattern with only the necessary bits of the captured response being updated while observing the full captured response. The theoretical and experimental analysis promises a substantial reduction in test cost for large circuits.

Scan-based designs effectively reduce test generation complexity and thus deliver improved fault coverage. Nevertheless, the traditional scan architectures suffer from increased test time and test data volume. The CircularScan architecture (Arslan and Orailoglu) provides a flexible environment for test cost reduction. The new scan design enables the use of the captured response of the previously applied test pattern as a template. The subsequent pattern is loaded by efficiently performing the necessary changes on the template through the functionality provided by the new architecture, conceptually exploiting the inherent low specified bit density of the test patterns. We explore the space of possible design alternatives built on the CircularScan architecture; the design alternatives are presented with accompanying test application methods. The experimental results indicate a substantial test cost reduction, reaching 90% levels. The proposed scheme is not only easily scalable but also promises further reductions in test cost when applied to large state of the art ICs.

Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propose two different methodologies for test cost reduction in scan-based designs. The first methodology improves on the Illinois scan architecture, aiming at reducing the high test cost of the test vectors that necessitate the serial test application mode. The second methodology employs on-chip serial transformations to generate an input stimulus that can be applied efficiently. The transformation-based methodology utilizes the proposed scan design to obtain the minimal cost input stimulus. The experimental results indicate that a substantial test cost reduction, reaching 90% levels, can be obtained.

Scan-based designs are widely used to keep test generation complexity within practical limits; nevertheless, scan-based design substantially increases test application time and test data volume. A novel scan-based design is proposed to reduce the test cost. The new scan-design exploits the low specified bit density of the test sets. The circular structure of the proposed architecture enables the use of the captured response of the previously applied pattern as a template for the subsequent pattern while allowing the full observation of the captured response. The functionality provided by the new architecture is utilized to update the template quickly to obtain the next pattern. The experimental results show a substantial reduction in test cost, reaching 90% levels.

Although the stuck-at fault model is the standard fault model. the frequently occurring faults in some technologies arc unintentional shorts, denoted as bridging faults. We outline a method that utilizes the information from the stuck-at fault model to accurately diagnose the bridging faults that affect two lines. The proposed method exploits the observation that the bridging fault response matches the stuck-at fault responses on the shorted lines for the failing test vectors and generates a candidate list that accounts for all failures. A further reduction in the size of the candidate set is achieved by extracting information from the test vectors that do not fail. The proposed method uses no layout information whatsoever. Nonetheless, the experimental results indicate that the bridging faults can be accurately diagnosed delivering a reduction in the sizes of the ambiguity sets and full capture of the offending bridging fault.

The exceedingly large size of fault dictionaries constitutes a fundamental obstacle to their usage. We outline a new method to reduce significantly, the size of fault dictionaries. The proposed method partitions the test set and a combined signature is stored for each partition. The new approach aims to provide high diagnostic resolution with a small number of combined signatures. The experimental results show a considerable decrease in the storage requirement of fault dictionaries.