By charging the implantable medical devices (IMDs) wirelessly, the need for frequent battery replacements on IMDs can be eliminated. With small chip area, linear battery chargers are suitable as charging circuits for IMDs. Due to the connection between the charging circuit and the output of the power receiver, the reverse current may flow out from the battery to the power receiver when the power transmitter stops power transmission, or the coils move apart. Conventionally, some switches were added to block the reverse current path. A new reverse current prevention circuit is proposed in this work for the linear battery charger. During reverse current prevention mode, the reverse current path is automatically blocked without the need of any additional switch. The experimental results from the fabricated silicon chip showed that the charging current during the normal constant current mode is 50.2 mA, with the battery voltage ranging from 3.3 V to 4.21 V. During the reverse current prevention mode, the total battery standby current is reduced to only 7.98 μA.

Integrated circuits (ICs) are susceptible to electrostatic discharge (ESD) events. Real-time detection and alerting of ESD events in semiconductor manufacturing environments is critical to control ESD. A new single-chip ESD event detector integrated with a logarithmic amplifier, magnitude discriminator, and time discriminator has been designed and fabricated in a 0.18-μm CMOS process. The amplitude of an ESD event can be detected and converted to 5-bit digital output codes. In contrast, the time duration of an ESD event can be converted to 3-bit digital output codes. The detected output codes can be transmitted to the ESD control center, enabling real-time ESD field control.

A wirelessly-powered biphasic current stimulator is proposed and designed for implantable neurostimulation. When receiving inductive coupling power at 13.56MHz from the power amplifier, the biphasic current stimulator delivers stimulation to the output channels automatically. The stimulation amplitude ranges from 100µA to 2.5mA, and the pulse width ranges from 10µs to 620µs. This chip was fabricated in the 0.18-μm CMOS process with a silicon area of 1764μm × 1115μm. In addition, a tiny PCB of 8mm × 9mm is utilized to implement the miniaturized stimulation device with the fabricated silicon chip. With the inductive RXcoil (LRX) and resonant capacitor (CRX), the stimulation function of this miniaturized wirelessly-powered biphasic current stimulator has been successfully verified in agar experiment.

A dual-configuration dual-mode 8-channel high voltage stimulator is proposed and designed for biomedical applications. Dual-configuration indicates the choice between a bipolar or monopolar structural arrangement, while dual- =mode refers to the selection between constant current or constant voltage stimulation. With supply voltages of 1.8 V, ±5 V, ±10 V, and ±15 V, the range of stimulus current is ±0.2 mA to ±10 mA with a 0.2 mA/step increment, and the range of stimulus voltage is ±0.2 V to ±10 V with a 0.2 V/step increment. The 8-channel stimulator chip has been fabricated in a 0.18-µm BCD process with a silicon area of 3570 µm x 1636 µm. Moreover, stimulus functions have been successfully verified through experiments in agar with Pt electrodes and in-vivo animal test on pig with DBS electrode.

In this paper, an analog front-end (AFE) local-field potential (LFP) acquisition unit with real-time stimulation artifact removal is proposed and verified for closed-loop deep brain stimulation (DBS) applications. The proposed acquisition unit is called the synchronized sample-and-hold stimulation artifact blanking (SSAB) AFE LFP acquisition unit. Both right-leg-driven (RLD) circuit and monopolar electrode-tissue impedance (ETI) measurement circuit associated with the AFE amplifier are also proposed. During closed-loop stimulations, the artifact removal is realized through the SSAB-IPC by blanking the AR-CCIA with a clock synchronized to the stimulation-enable signal and holding the amplifier at its state before stimulation through a sample-and-hold operation. After stimulation, the acquisition unit can quickly recover from the holding state back to the LFP recording state to reduce the discontinuity in LFP recording. The proposed acquisition unit was fabricated in 0.18-$\mu {\mathrm{ m}}$CMOS technology. With the RLD circuit, the measured CMRR is 124– 145 dB in the signal bandwidth. The fabricated monopolar ETI measurement circuit has a measurement error less than 8.3% with an extra power consumption of$2.65 \mu \text{W}$. The experimental results have shown that the proposed SSAB AFE LFP acquisition unit is feasible for the integration of SoCs in real-time closed-loop DBS systems for various applications.

Electrostatic discharge (ESD) protection design for high-linearity single-pole double-throw (SPDT) transmit/receive switch (T/R switch) at 0.9/1.8 GHz GSM band was proposed and verified in a standard 0.18-μm CMOS process. The SPDT CMOS T/R switch was implemented with body-floating technique, multi-stacked structure, and series-shunt topology to obtain low insertion loss, high power handling capability, and good isolation. With the proposed ESD protection design, the T/R switch can sustain human-body-model (HBM) ESD voltages of 3.5 kV under the positive-to-VSSstress and 5 kV under the negative-to-VSSstress. Experimental results including ESD characteristics, RF performance, and failure analysis are presented.

This paper presents the closed-loop neural disorder control concept and some design considerations. Two architectures of closed-loop neuromodulation for Parkinson's disease and epileptic seizure are proposed. One is a closed-loop deep brain stimulator, which meets the IEC 60601-1 standard. The other one is an implantable SoC for epileptic seizure control, which is verified by animal experiment.

All wireless communication products must meet the reliability specifications during mass production. To prevent from electrostatic discharge (ESD) damages, the ESD protection designs must be added at all input/output pads in chip. Some ESD protection designs with low parasitic capacitance for radio-frequency (RF) applications are reviewed in this paper. Besides, a novel ESD protection design is proposed and realized in a 65nm CMOS process to protect the wideband RF circuits. In this work, diodes are used for ESD protection and inductors are used for high-frequency performance fine tuning. Experimental results of the test circuits have been successfully verified.

A biomedical stimulator with four high-voltagetolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-μm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.

A new power-rail ESD clamp circuit is proposed and verified with consideration of the gate leakage issue in 65-nm CMOS technology. The proposed circuit can reduce the total leakage current of the traditional power-rail ESD clamp circuit in two orders of magnitude. Moreover, the proposed circuit reduces the required silicon area by boosting the capacitor with a current mirror. The measured leakage current of the proposed power-rail ESD clamp circuit is 220nA (VDD= 1V, T=25°C), much lower than the 20.55μA of the traditional design. In addition, the required area for the proposed design is 50μm × 30μm, which is a 40% reduction in silicon area to the traditional one, that can sustain the HBM (MM) ESD stress of 3.5kV (250V).

Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.

In this work, a new design of the ESD-transient detection circuit with the n-channel metal-oxide-semiconductor (nMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been proposed and verified in a 65nm 1.2V CMOS process. As compared to the traditional RC-based ESD-transient detection circuit, the layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long turn-on duration under the ESD stress condition, as well as better immunity against mis-trigger or transient-induced latch-on event under the fast power-on and transient noise conditions.

With high normal operating voltages, latchup is an important reliability issue for high-voltage (HV) ICs. Harsh operating environments further deteriorate the transient-induced latchup (TLU) immunity of HV ICs. High immunity against TLU has therefore become an important reliability factor of HV ESD protection circuits. In this work, a novel ESD protection circuit with HV silicon controlled rectifier as the main ESD protection element has been proposed. The new proposed ESD protection circuit has been verified in a 0.5-nm 16-V Bipolar CMOS DMOS process. Experimental results showed that the new proposed ESD protection circuit has high TLU immunity of +220V/-295V and high human body model (machine model) ESD robustness of 4.5 kV (500V) at the same time.

With the consideration of low standby leakage in nanoscale CMOS processes, a new 2×VDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ~200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mum 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (It2) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25degC in the silicon chip. Moreover, it can achieve ESD robustness of over 8 kV in human-body-model (HBM) and 750 V in machine-model (MM) ESD tests, respectively.

Waffle-structured SCR (silicon-controlled rectifier) has been studied as an effective on-chip ESD (electrostatic discharge) protection device for CMOS RF (radio-frequency) circuits. In this work, a novel on-chip ESD protection strategy using the waffle-structured SCR is proposed and co-designed with a CMOS UWB (ultra-wideband) PA (power amplifier). Before ESD stress, the RF performances of the ESD-protected PA have been demonstrated to be as well as that of the unprotected PA. After ESD stress, the unprotected PA was seriously degraded, whereas the ESD-protected PA was keeping the performances well.

A new 2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without suffering gate-oxide reliability issue is proposed, which is one of the key mixed-voltage I/O cells in a cell library. The proposed circuit is realized with only thin gate-oxide devices with floating n-well technique. The proposed 2xVDD-tolerant crystal oscillator circuit has been designed and verified in a 90-nm 1-V CMOS process to serve 1/2-V mixed-voltage interface applications.

In the nanometer-scale CMOS technology, the gate-oxide thickness has been scaled down to support a higher operating speed under a lower power supply (1timesVDD). However, the board-level voltage levels could be still in a higher voltage levels (2timesVDD, or even more) for compatible to some earlier interface specifications in a microelectronics system. The I/O interface circuits have been designed with consideration on the gate-oxide reliability in such mixed-voltage applications. In this work, a new mixed-voltage crystal oscillator circuit realized with low-voltage CMOS devices is proposed without suffering the gate-oxide reliability issue. The proposed mixed-voltage crystal oscillator circuit, which is one of the key I/O cells in a cell library, has been designed and verified in a 90-nm I-V CMOS process to serve 1/1.8-V mixed-voltage interface applications.

This paper presents a new tracking circuit design without standby leakage current issue for 2.5V/3.3V tolerant I/O buffer, which is suitable for the I/O cells in the mixed-voltage applications with different driving capabilities. One set of mixed-voltage I/O cell with the new proposed 2.5V/3.3V tolerant I/O buffer circuit has been designed and drawn in a 0.13-/spl mu/m salicided CMOS process. The new tracking circuit can be also applied in other CMOS processes to serve different mixed-voltage I/O interfaces.

A new matching design of low-noise amplifier (LNA) with ESD protection is proposed and implemented in an ESD-protected LNA, which manipulates the parasitic capacitance of ESD protection device as a core part of LNA matching network. Without significant degradation on RF performance, 4.5-kV human-body-model (HBM) and 250-V machine-model (MM) ESD levels can be achieved. The low RF-performance degradation and high ESD immunity can be simultaneously realized in a simple matching structure without extra circuit components dealing with ESD parasitics in a multi-GHz LNA.

A LVDS receiver with new data recovery design for flat-panel-display (FPD) link is presented. The new delay-selecting technique is used in LVDS receiver to reduce the circuit complexity and to save chip power for cost-efficient applications. The proposed LVDS receiver with an operation data rate of 1.25 Gb/s has been successfully verified in a 0.13-/spl mu/m CMOS process, which can fully support the operation of FPD link with UXGA resolution.

An on-chip ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-precision applications. A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices has been developed to keep the total input capacitance almost constant (within 1% variation), even if the analog signal has an input dynamic range of 1 V. The device dimension (W/L) of the ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (/spl mu/m//spl mu/m) in a 0.35 /spl mu/m silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only /spl sim/1.0 pF (including the bond pad capacitance) for high-frequency applications.

A new diode string design with very low leakage current is proposed for using in the on-chip power supply ESD (electrostatic discharge) clamp circuits. Three traditional designs of the stacked diode strings used in the power supply ESD clamp circuits are also fabricated in the same test chip to verify the improvement of this new design. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the leakage current of this new proposed diode string with 6 stacked diodes under a 5 V (3.3 V) forward bias condition can be controlled below 2.1 (1.07) nA at an environment temperature of 125/spl deg/C. The blocking voltage of this new diode string design with NCLSCR can be linearly adjusted by simply changing the number of the stacked diodes in the diode string for application across the power lines with different voltage levels to achieve a whole-chip ESD protection scheme.

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.

There is one LVTSCR (Low Voltage Trigger SCR) device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in a complementary style to offer effective and direct ESD discharging paths from the input or output pads to V/sub SS/ and V/sub DD/ powerlines. The DC switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it has an excellent ESD protection capability in a smaller layout area.