Yi Zhang 0092

dblp:64/6544-92 · DBLP profile ↗
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5ranked-venue papers
2as first author
5since 2021 · last 2025
0000-0003-2888-4736ORCID · verified

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Systems, architecture and hardware · 4 · 2 first-author · 4 since 2021
YearPublicationVenuePosition
2025 A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25-71GHz for Multi-Band 5G NR
abstract
A tri-mode mixer supporting the 5G NR standards over 24.25--71GHz is presented. The harmonic-selection technique reduces the local oscillator (LO) frequency range and power consumption. Besides, the proposed multiphase LO rejects unwanted harmonics. Fabricated in a 65nm CMOS process, this work consumes 12-21mW power under a 1V supply. It presents more than 20dB rejections to the undesired harmonic components at all operation bands. The required LO frequency range is only 10GHz.
Dongfan Xu, Minzhe Tang, Yi Zhang 0092, Zheng Li 0021, Jian Pang, Atsushi Shirane, Kenichi Okada 0001
ASP-DAC3
2025 A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data Rate
abstract
An 8-Element 28-GHz time-division MIMO beamformer supporting 4x4 MIMO is presented. A fast-switching phase shifter is utilized to realize Nyquist-rate beam switching to lossless receive multiple beams by reuse single RF signal path. A prototype fabricated in 65nm CMOS achieves 64-QAM 4x4 MIMO reception in OTA measurement using four 5G NR spatial data streams with 400MHz channel bandwidth.
Yi Zhang 0092, Minzhe Tang, Zheng Li 0021, Dongfan Xu, Kazuaki Kunihiro, Hiroyuki Sakai 0009, Atsushi Shirane, Kenichi Okada 0001
ASP-DAC1
2024 A 24-71-GHz Tri-Mode Mixer Using Harmonic Selection for Multi-Band 5G NR
abstract
This paper presents a tri-mode band-selection CMOS down-conversion mixer supporting the 5G NR standards over 24.25–71 GHz. The harmonic-selection technique reduces the required local oscillator (LO) frequency range and power consumption. The second-harmonic selection mode works for the 39-GHz and 47-GHz bands, while the fundamental-selected and third-harmonic selection modes operate for the 28-GHz and 60-GHz bands, respectively. Besides, in cooperation with the proposed multi-phase LO, the mixing components behave destructively for the undesired harmonics and constructively for the desired component, which shows the rejection of unwanted harmonics. Fabricated in a 65-nm CMOS process, this work presents flat conversion gain and more than 20-dB rejections to the undesired harmonic components at all operation bands. The required LO frequency range is only 10 GHz. Occupying a core area of 0.0077 mm2, the proposed mixer consumes power of 12-21 mW in three modes under a 1-V supply.
Dongfan Xu, Minzhe Tang, Yi Zhang 0092, Zheng Li 0021, Atsushi Shirane, Kenichi Okada 0001
ISCAS3
2022 Millimeter-Wave CMOS Phased-Array Transceivers for 5G and Beyond
abstract
This work first discusses the future directions of millimeter-wave wireless communication, based on Shannon and Friis equations. Afterward, 28-GHz and 39-GHz phased-array transceivers realized by 65nm CMOS technology are introduced, which are designed for 5G and beyond. The 28GHz phased- array transceiver is designed based on a neutralized bi-directional technique. The required chip area for the element transceiver is reduced to half. A cross-pol. leakage canceller is also implemented along with the transceiver to suppress the crosspol. leakage. Therefore, the dual-polarized 28-GHz phased-array module is capable to improve the wireless data with dual- polarized MIMO (DP-MIMO) configuration even under severe polarization coupling and rotation conditions. The measured DP-MIMO EVMs are 3.4% in both 64-QAM and 256-QAM. The 8-element 39GHz phased-array transceiver is also designed based on the compact bi-directional architecture. The Doherty technique is utilized in TX mode to increase the power efficiency at power backoff region. A 64-element transmitter array realizes a saturated output EIRP of 55.2dBm. To improve the phased- array performance under digital pre-distortion (DPD), an inter- element mismatch compensation technique is further employed. By utilizing the proposed mismatch compensation, the measured 64-QAM OFDMA-mode EVM and ACLR with the shared-look- up-table (shared-LUT) DPD are improved from -22.4dB to - 25.0dB and from -28.7dBc to -32.1dBc, respectively.
Kenichi Okada 0001, Jian Pang, Atsushi Shirane, Zheng Li 0021, Yi Zhang 0092, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro
PIMRC5
2021 28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver
abstract
A phase shifter with temperature compensation for 28GHz phased-array TRX is presented. A precise low-voltage current reference is proposed for the IDAC biasing circuit. The total gain variation for a single TX path including phase shifter and post stage amplifiers over -40°C to 80°C is only 1dB in measurement and the overall phase error due to temperature is less than 1 degree without off-chip calibration.
Yi Zhang 0092, Jian Pang, Kiyoshi Yanagisawa, Atsushi Shirane, Kenichi Okada 0001
ASP-DAC1