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Chien-Chih Huang

dblp:64/783 · DBLP profile ↗
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9ranked-venue papers
5as first author
1since 2021 · last 2021
0000-0003-2039-8354ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-author · 1 since 2021Artificial intelligence and machine learning · 2Databases, data management, data science and information retrieval · 2Human-computer interaction and ubiquitous computing · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 62% Electronic design automation · 38%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.312017
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Integrated circuit design › analog and mixed-signal circuits › data converters
analog-to-digital converter
0.312017
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Integrated circuit design › analog and mixed-signal circuits › analog VLSI
capacitor matching
0.312017
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Electronic design automation
physical design
0.312017
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Electronic design automation › physical design
placement
0.312017
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Integrated circuit design
parasitic capacitance
0.112017
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017

Methods — techniques the papers use, named apart from their topics

partition-centering-based symmetry placement · 0.3
YearPublicationVenuePosition
2021 On Compare-and-Swap Optimization for Fully Homomorphic Encrypted Data
abstract
Fully homomorphic encryption (FHE) is a powerful scheme that can be applied to perform computations directly on encrypted data for ensuring the security of cloud computing. Using the concept of aggregate plaintext, this paper explores how to optimize the compare-and-swap operation, commonly used for sorting and searching in cloud computing, for FHE data. The resulting performance is optimized by properly arranging the operand locations, corresponding to the desired plaintext slots, and then scheduling a sequence of fundamental homomorphic operations designed to accomplish the targeted operation. Moreover, the hypercube plaintext slot structure is considered to efficiently manipulate the required shift operation and merge multiple operands in an aggregate plaintext. Analytical results show that the number of homomorphic multiplication and shift operations needed in the proposed compare-and-swap operation are logn + 4 and 2logn + 1, respectively, for n-bit data, which is at least 16 times faster than related works for n = 64. Applying the proposed scheme can not only reduce the size of required FHE data, but also improve the total computation time of the chosen operation.
Chien-Chih Huang, Jyun-Neng Ji, Ming-Der Shieh
ISCAS1
2017 PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays
abstract
Capacitor matching influences linearity performance, which is a critical measure of analog-to-digital converters (ADCs). Various placement techniques have been proposed to eliminate both systematic and random mismatches of capacitor pairs. However, a placement technique that eliminates capacitor mismatches may not result in good linearity performance for successive-approximation-register ADCs because their linearity performance is related to the accuracy of their binary-weighted continued ratio. This paper addresses the critical problem of placement estimation based on ratio mismatch M, overall correlation coefficient L, and performance metrics. A low M and a high L value do not imply higher linearity performance. Therefore, we propose a partition-centering-based symmetry placement algorithm for the layout considering parasitic capacitance matching. The experimental results show that the proposed placement approach can achieve higher linearity performance and a shorter placement generation time compared with the conventional approach.
Chien-Chih Huang, Jwu-E Chen, Chin-Long Wey
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2015 Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs
abstract
The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch. Paralleling unit capacitance (UC) with a common-centroid structure can alleviate the random mismatch errors. The complexity of generating an optimal solution to the UC placement problem is extremely high, let alone if both placement and routing problems are to be optimized simultaneously. This article evaluates the performance of the UC placement generated in an existing work and proposes an alternative UC placement to achieve optimal ratio mismatch M and better linearity performance of SAR ADC design. Results show that the proposed UC placement achieves a ratio mismatch of M = 0.695, the effective number of bits ENOB = 8.314 bits, and the integral nonlinearity INL = 0.816 LSB (least significant bits) for a 9-bit SAR ADC design.
Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo
ACM Trans. Design Autom. Electr. Syst.1
2014 Knowledge withholding intentions in teams: The roles of normative conformity, affective bonding, rational choice and social cognition
Crystal Han-Huei Tsay, Tung-Ching Lin, Jeewhan Yoon, Chien-Chih Huang
Decis. Support Syst.4
2013 Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits
abstract
Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimization criterion that quickly determines if the placement is optimal. The optimization criterion leads to the development of the concepts of C-entries and partitioned subarrays which can significantly reduce the searching space for finding the optimal/near-optimal placements on a sufficiently large array size.
Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo
ACM Trans. Design Autom. Electr. Syst.1
2010 Withholding effort in knowledge contribution: The role of social exchange and social cognitive on project teams
Tung-Ching Lin, Chien-Chih Huang
Inf. Manag.2
2009 Understanding social loafing in knowledge contribution from the perspectives of justice and trust
Tung-Ching Lin, Chien-Chih Huang
Expert Syst. Appl.2
2008 Understanding knowledge management system usage antecedents: An integration of social cognitive theory and task technology fit
Tung-Ching Lin, Chien-Chih Huang
Inf. Manag.2
2004 Foundation Analysis of Emotion Model for Designing Learning Companion Agent
abstract
This paper proposes the architecture of learning companion agent with facial expression of emotion. Based on ABC and ToK architecture, the emotion agent architecture contains five modules to realize the interaction in the world. A particular part of this research is the transition between emotion space in emotion module and facial expression space in facial expression module. Using this transition and those five modules, a small experiment Web site with emotion agent demonstrates the facial expression of the agent and its emotion tracks.
Chien-Chih Huang, Rita Kuo, Maiga Chang, Jia-Sheng Heh
ICALT1