Hybrid cache architectures (HCAs) containing both SRAM and non-volatile memory (NVM) have been proposed to overcome the disadvantages of NVM-based cache architecture. Most previous works have concentrated on managing write-intensive blocks by storing these blocks to SRAM to reduce the number of the write operations to NVM. However, they have not focused on reducing linefill operations which also occupy a large portion of overall NVM write counts in chip-multiprocessor (CMP) environments. This paper proposes an NVM way allocation scheme, taking into account the NVM linefill counts as well as cache miss rate and the NVM write hit counts during victim selection. Three metrics are introduced to estimate the effectiveness of NVM way allocation: Miss counts change (ΔM), write counts change (ΔW), and NVM write counts change (ΔNVMW). An algorithm to minimize the write counts of NVM based on these metrics is proposed as well. Our experimental results show that dynamic energy consumption is reduced by 37.5 percent on average.

Spin-transfer-torque RAM (STT-RAM) is one of the emerging nonvolatile memories for last-level cache (LLC) featuring high density and low leakage. However, long latency for the write operation, which comes from the characteristics of nonvolatility, degrades performance when STT-RAM is employed as LLC. To overcome this problem, we revisit the existing cache update policy and propose a new cache update policy to exploit the asymmetric write characteristics of STT-RAM. In our proposal, the data are written into a fast writeable block, regardless of the original position when the block arrives at the LLC. This paper proves the efficiency of our update policy based on analytical models and gives detailed information for implementing the policy. The experimental results show our scheme reduces slow writes by 77.6%, which leads a 31.1% reduction in write latency.

Existing hybrid cache architecture (HCA) studies have concentrated on managing write-intensive blocks to relieve the write pressure on Non-volatile memory (NVM). However, they have overlooked that the capacity of NVM is also one of important factors affecting the number of write accesses to NVM. This research investigates the relationship between the size of NVM and the write counts of NVM to efficiently design a new algorithm to reduce the write counts of NVM in HCA. Based on the analysis, it is revealed that adjusting the capacity of NVM can decrease write requests to NVM if the miss rate does not grow. This discovery leads to the necessity of NVM capacity management policy such that the size of NVM is dynamically adjusted according to the demand of applications. To implement the policy, we propose a dynamic way adjusting algorithm which dynamically monitors the optimal number of NVM ways using the stack property and disabling the unnecessary NVM ways. The experiments are conducted for two HCAs with STT-RAM and PCM. The results show that proposed management policy reduces the write accesses to STT-RAM by 77.6% and PCM by 79.6%.