This research vision and challenges paper focuses on microprocessor design and activity-recognition data processing for medical devices in student-athlete health care. Sports are the second leading cause of mild traumatic brain injury (mTBI) for people aged between 15 and 24 years. Significant work has been done in the use of sensors to determine the linear and rotational acceleration of head impacts, and their potential correlation to concussions. However, recent studies have shown that subconcussive trauma may be a better indicator of future risks, such as impaired cognitive, motor, and sensory functions, as well as loss of control of emotion and behavior. Therefore, the current reactive and hospital-centered approach where waiting until a concussion has been diagnosed before providing quality care to student athletes is insufficient. Our project will enable a transformation in student-athlete healthcare through the design of sensors towards a preventive, proactive, and evidence-based approach for assessing and mitigating the risk of long-term brain injury. Research and develop improvements towards a next-generation form-factor xPatch device with radio transceivers for secure and efficient processing of head impact data, while considering transmission range vs. power consumption, receiver sensitivity, data rate, start-up time, latency, capacity, and cost. We will enhance X2 Biosystems's currently existing Injury Management System data platform through development and integration of on-chip data processing towards real-time recording and secure wireless transmission of impact data. Integration of 6 degree-of-freedom support vector data will enable improved machine learning-based principal component analysis of head impact data. In order to provide real-time integration of on-chip machine learning and cloud-based impact classification algorithms, we will also develop an encrypted 915MHz ISM band radio solution for secure and reliable transmission of impact data for real-time interpretation by athletic trainers or certified medical professionals on the sidelines within athletic environments.

Production of cost-effective secure integrated chips, such as smart cards, requires hardware designers to consider tradeoffs in size, security, and power consumption. To design successful security-centric designs, the low-level hardware must contain built-in protection mechanisms to supplement cryptographic algorithms, such as advanced encryption standard and triple data encryption standard by preventing side-channel attacks, such as differential power analysis (DPA). Dynamic logic obfuscates the output waveforms and the circuit operation, reducing the effectiveness of the DPA attack. For stronger mitigation of DPA attacks, we propose the implementation of adiabatic dynamic differential logic (ADDL) for applications in secure integrated circuit (IC) design. Such an approach is effective in reducing power consumption, demonstrated using HSPICE simulations with 22-nm predictive technology. The benefits of our design are demonstrated by comparing instantaneous power waveforms and observing the magnitude of differential power spikes during switching events. First, simulation results for body biasing on subthreshold adiabatic inverters show an improvement in differential power up to 43.28% for similar inverters without body biasing. Then, a high-performance ADDL is presented for an implementation in high-frequency secure ICs. This method improves the differential power over previous dynamic and differential logic methods by up to 89.65%. Finally, we propose a body-biased ADDL for ultralow power applications. Simulation results show that the differential power was improved upon by a factor of 199.16.

Programmable reversible logic is emerging as a prospective logic design style for implementation in low power, low frequency applications where minimal impact on circuit heat generation is desirable, such as mitigation of differential power analysis attacks. Adiabatic logic is an implementation of reversible logic in CMOS where the current flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized. Recent advances in dual-rail adiabatic logic show reduction in average and differential power, making this design methodology advantageous in applications where security is the primary design metric and operating frequency is slower, such as Smart Cards. In this paper, we present an algorithm for synthesis of adiabatic circuits in CMOS. Then, using the ESPRESSO heuristic for minimization of Boolean functions method on each output node, we reduce the size of the synthesized circuit. Our approach correlates the horizontal offsets in the permutation matrix with the necessary switches required for synthesis instead of using a library of equivalent functions. The synthesis results show that, on average, the proposed algorithm represents an improvement of 36% over the best known reversible designs with the optimized dual-rail cell libraries. Then, we present an adiabatic S-box which significantly reduces energy imbalance compared to previous benchmarks. The design is capable of forward encryption and reverse decryption with minimal overhead, allowing for efficient hardware reuse.