The post-silicon integrated circuits (IC) testing is a very expensive process, especially in automotive industry where chip functionality has to be guaranteed by verifying multiple electrical parameters over a wide range of operating conditions. However, some costs can be avoided by reducing the amount of redundant tests, as certain parameters may exhibit a predictable behavior on the operating conditions variation. This paper presents a comparison between three approaches that use temperature parameters behavior for reducing the number of IC tests. The methods are tested on a production dataset consisting of 25 parameters and 300000 chips, results showing that the best method saves approximately 12 % of the measurements.

Analog and Mixed Signal circuit sizing with large-scale parameters requires a lot of simulations, especially in non-linear topology where large-signal analysis is a need. Reducing the number of simulations and in general the total design cycle time, is the main objective for optimal sizing of complicated circuits. In this work a circuit sizing automated design methodology is presented using the hybrid dual annealing and Nelder–Mead algorithm, significantly reducing the design cycle time and the required number of transient simulations. A customized hybrid algorithm environment using Dual Annealing and Nelder–Mead is developed where the optimization process is divided into different optimization sub-steps. The proposed hybrid algorithm based method achieves rapid convergence to the needed circuit performance specification. It uses combinations of direct search algorithms to separate metric evaluation accelerating the performance specifications convergence speed in a large parameter space. A complicated non-linear topology like a product level low-dropout (LDO) regulator, in 180 nm process node, with 30 parameters is used as the circuit vehicle to verify the proposed methodology. The sizing process converged with less than 1700 simulations having as input just the circuit schematic with no prior sizing knowledge. Sub optimization is also performed focused on each analysis type - DC, AC and transient, with a focus on reducing the number of transient simulations. The proposed combined algorithm method achieved 31 % faster convergence speed compared to the state-of-the-art methods and handles efficiently each simulation analysis. • Analog circuits have metrics that in general need different simulation types for evaluation. A number of combinations of algorithms are proposed to optimize different sub-stages of the process. • A large LDO circuit is used as a base for the demonstration and comparison of the methodologies, with 30 parameters and 10 performance metrics. • Significant number of transient analysis simulations is reduced (31%), keeping the result within the error limits, using the best performing hybrid algorithms that include Nelder–Mead, Dual Annealing, NSGA-II, etc.

Designing power electronic switches in a timely manner is essential for a wide range of electrical applications. The challenge arises when determining the acceptable design parameters from the product definition space that lead to a functioning application. Creating a well-defined product definition space can help reduce design cycle time and minimize the risk of design failure or non-compliance with requirements. In response to this, we propose a machine learning-based framework to create this space with substantially less simulations in comparison to exhaustive and optimization-based methods. This is particularly beneficial in higher dimensions where running numerous simulations may not be feasible. We applied this approach to generic silicon power switches within a half-bridge motor drive application simulation, defining borders that closely match-above 98%-to the borders of the product definition space. In this use case, the need for simulations is reduced by a factor of five, while still meeting all operating conditions and requirements.

This paper introduces several solutions for multivariate extension of a previously designed single response adaptive pre-silicon integrated circuit verification approach employing machine learning algorithms. These techniques aim to achieve the most accurate identification of worst-case circuit behavior through simultaneously modeling multiple electrical parameters (EP). The effectiveness of the proposed methods was validated through extensive testing on a large and diverse set of synthetic test functions that intend to replicate the behavior of real circuits. The algorithms consistency and accuracy are also validated on a real Low Dropout Voltage Regulator (LDO) circuit.

Circuit sizing for designs with many design variables and responses is a complex task that requires highly experienced and creative designers to invest precious time in trial and error, routine work. In addition, sizing the circuit while also taking into account PVT (process, voltage, temperature) variation corners increases the complexity further. To simplify such tasks, designers select the most unfavorable PVT corner in advance (leveraging their expertise), perform circuit sizing for this condition, and finally verify the resulting design in all PVT corners. This procedure might generate designs that fail the specifications in other PVT corners leading to more design-verification iterative loops. Recent years brought machine learning (ML) and optimization techniques to the field of circuit design, with evolutionary algorithms and Bayesian models showing good results for automated circuit sizing. However, these methods can still require an unfeasibly large number of simulations, especially if taking into account several PVT corners. In this context, we introduce a methodology that uses surrogate ML models to perform PVT variation-aware circuit sizing. We propose to dynamically select the worst PVT corners and take them into account when sizing the circuit. In addition, we explore the best ways to model process corners with Gaussian Processes, leading to more than 10x improvements for such surrogate models. We evaluate the proposed corner management method on two voltage regulators showing different levels of complexity and highlight that it enables finding feasible solutions 2x faster when compared to baseline algorithms which optimize in all PVT corners. In addition, the quality and diversity of the proposed solutions are significantly higher by one to three orders of magnitude in terms of population hypervolume.

The paradigm shift of the digital transformation of the Industry 4.0 towards top level graphical representations of system and product requirements make early digital representations more and more common, often in the form of SysML models. In later process development phases, Virtual Prototypes are often used to facilitate early product learning, test case enabling and debug. This paper discusses the various aspects of Virtual Prototyping starting from very abstract models down to hardware prototyping and expected modelling effort and benefit based on examples out of the automotive smart power and sensor world.

Manual sizing of analog circuit specifications has become challenging owing to their ever-increasing complexity. Especially for innovative, large-scale circuit designs with numerous design variables, operating conditions, and conflicting objectives to optimize, analog designers must run time-consuming simulations for several weeks to find the optimum configuration. Recently, machine learning and optimization techniques have been applied in the field of analog circuit design, wherein evolutionary algorithms and Bayesian models have shown good results for circuit sizing tasks. In this context, we introduce multi-objective optimization based on differential evolution and Bayesian inference (MODEBI)—a design optimization method based on generalized differential evolution 3 (GDE3) and Gaussian processes (GPs). The proposed method can perform sizing for complex circuits that require optimization of many design variables and conflicting objectives. Although state-of-the-art methods reduce multi-objective problems to single-objective optimization and potentially induce a priori bias, the proposed method searches directly over the multi-objective space using Pareto dominance and ensures that designers are provided with diverse solutions to choose from. To reduce optimization time, we propose using GPs to model the circuit and employing this surrogate model to preselect candidates. However, this results in a more complex offspring selection process, and the diversity in population survival must be specifically addressed. This paper proposes several solutions to these problems, resulting in multiple MODEBI variations. To the best of our knowledge, this is the first method that specifically addresses solution diversity and simultaneously focuses on minimizing the number of simulations required to obtain feasible configurations. The evaluation performed on two voltage regulators with different complexity levels showed that the proposed offspring selection method and survival policy can obtain highly diverse feasible solutions considerably faster than GDE3 or Bayesian optimization-based algorithms.

There is a consistent dependence between integrated circuits (ICs) performance parameters and manufacturing process variations and capturing it at an early development phase represents a major ongoing topic in the semiconductor industry. Typically, this is addressed by the means of Monte Carlo (MC) simulations, where the device model parameters are randomly instantiated according to the technology variations based on a predefined nominal process. Thus, the resulted simulation data can only capture the effect of these variations. This offers little or no insight on the performance’s sensitivities to specific process variations or on the effect of altered statistical technology properties, as it may be the case of process drift or fab-to-fab migration. This article proposes a methodology for modeling the dependency of the device performances (i.e., electrical parameters—EPs) with the influential technology parameters (i.e., process control monitor parameters—PCMs), at an early stage (preSilicon). Using a set of standard MC co-simulations of PCM structures and the circuit schematics (to maintain consistent process variation), it employs a feature selection step to choose the influential PCMs and it trains a machine learning regression algorithm. Both are wrapped up in a Bayesian optimization (BO) framework to find the optimal feature set and the regression hyperparameters. The obtained regression model can explain the functional dependency of the EP on the influential PCMs. Thus, it directly enables sensitivity analysis (SA) to process variation and parametric yield prediction of the IC, as it will be illustrated for the case of an experimental Infineon Technologies product.

This paper proposes a pole-placement method for tuning the discrete PID control of a DC-DC Buck converter that ensure specific time-domain performances when a step disturbance in the input voltage or load is applied. The control is also designed to reduce steady-state oscillations caused by the digital implementation nonlinearities of the control loop. The effectiveness of the method is verified on both simulation and experimental levels.

This paper proposes a method for speeding-up the verification process of integrated circuits, featuring waveform clustering of circuit response signals. The main objective is to automatically separate the signals into distinct groups that potentially exhibit visual similarities in order to aid the visual inspection/verification. As a first step, the proposed method extracts SIFT-like features by finding stable points of the signal over the scale space and computing robust descriptors able to describe their neighborhood. The resulted descriptors are quantized in order to be used in the clustering process as bag-of-words histograms. We demonstrate the validity of our method on a circuit waveform database containing several thousands of signals belonging to ten electrical tests.

This paper proposes a method for explanation of the lifetime variation of power devices using data from different test stages. Understanding the lifetime variation is very useful in qualification, as well as in the characterization process, in order to improve the robustness of the power devices or to estimate more accurately the minimum guaranteed lifetime. Moreover, it helps design engineers better understand the root causes of the lifetime variation and use this knowledge to improve the performances of new power devices. In the proposed methodology, the variation of the lifetime is explained by the electrical parameters, measured before the stress-test. The Sensitivity Analysis presented here has the advantage of being simple and fast. It can be applied even when the number of test-runs is less than the number of factors. Moreover, it reveals not only linear correlations, but also quadratic effects and 2nd and 3rd order interactions. Eventually, the method provides the top of the most relevant electrical parameters which explain the lifetime variation. The validation of this approach has shown that 72% of the lifetime variation can be explained by the initial values of 5 electrical parameters.

The standard metrics for integrated circuits' analysis and characterization in production processes usually assume that the process under investigation is characterized by a normal distribution. However, the data met in practice are not always normal and the yield estimates may be inaccurate. In this paper we propose estimating the yield by using a distribution fitting flow. The selected distribution types proved to estimate more accurate yields, with lower variance of the estimates. The distribution models proved to be a reliable tool also for integrated circuits' characterization in terms of specification limits' determination.

The paper proposes a methodology for lifetime estimation of power devices at given applications operating conditions. The active cycling of power devices requires huge testing-time, because the process cannot be accelerated. For this reason, most often, the manufacturers provide information about the lifetime of power devices only for a few specific operating conditions. Most of the current methods are based on the junction temperature swing, which is very difficult to be measured or estimated. Instead, we propose an approach that, based on a few measurements of lifetime at given ambient temperatures, load currents and repetitive energies, is able to make lifetime prediction at any other set of operating conditions. The validation of the method was done by performing lifetime predictions in other operating conditions than those used for fitting the prediction function (metamodel) and it has shown a maximum relative error of 20%. With the proposed methodology, lifetime estimations of power devices can be made in the space of applications operating conditions, using optimal testing resources.

During the development process of a semiconductor-based product several types of results are generated, often in large volumes, e.g. simulation or test measurements. These have to be processed and can then be used as a reusable knowledge base for further experiments/developments. Hence, to manage such knowledge from various data sources, it is not sufficient to use classical data analysis methods. A compressed representation of this information, showing only what is important with respect to the systems performance, is desirable. We develop a method to support the combination of information from different sources and to represent it. The concept is based on cascading metamodels: The outputs of metamodels become inputs to subsequent metamodels, and mathematical composition operators can be generated for this concatenating procedure. This method is applied to a power module in order to perform sensitivity analysis on the combined metamodel.

In this paper we present a concept for assessing the robustness of automotive smart power ICs through lab measurements with respect to application variance and parameter spread. Classical compliance to the product specification, where only minimum and maximum values are defined, is not enough to assess device robustness since complex transients of application components cannot be defined within single specification parameters. That is why application fitness becomes a necessary task to reduce device failures, which may occur in the application. One solution would be to enhance traditional lab verification methods with a concept that considers application and parameter spread. This innovative concept is demonstrated on an electronic throttle control application. It has been emulated in real-time, including power amplification and application-relevant parameters. Monte Carlo experiments were carried out within the application space to evaluate the influence of parameter spread on selected system characteristics. Finally, an appropriate metric was used to quantify the robustness of the micro-electronic device within its application.

In this paper we propose to exploit so called Mission Profiles to address increasing requirements on safety and power efficiency for automotive power ICs. These Mission Profiles constrain the required device performance space to valid application scenarios. Mission Profile data can be represented in arbitrary forms like temperature histograms or cumulated drive cycle data. Hence, the derivation of realistic verification scenarios on device level requires the generation of environmental properties as e.g. temperatures, board net conditions or currents. For the assessment of real application robustness we present a methodology to extract finite state machines out of measured vehicle data and integrate them in Mission Profiles. Subsequently Markov processes are derived from these finite state machines in order to automatically generate Mission Profile compliant test scenarios for the design and verification process. As a motivating example we show industry fault cases in which missing application fitness to power transient variations finally results in device failure. Verification results based on lab data are outlined and show the benefits of a fully mission profile driven IC verification flow.

With the advent of the ISO 26262 it became crucial to prove that electrical and electronic products delivered into safety-related automotive applications are adequately safe. For this purpose safety goal violations due to random hardware failures need to be evaluated. In order to gain evident results for argumentation within the evaluation, a fault injection based approach is utilized. Potential risk scenarios are initiated by injection of analog and digital faults into the heterogeneous behavioral model which comprises the safety-related hardware. For fault injection in heterogeneous models, we propose analog saboteurs, designed in VHDL-AMS, by which amongst electrical or mechanical, diverse energy domain analog hardware faults may be injected. For demonstration of this approach, a hardware model, comprising lithium-ion battery cells with a cell balancing module and safety-related circuitry is used.

As systems and electrical and electronic devices are becoming more and more complex, the number of requirements is increased accordingly. Therefore, the organization, the processing and the verification of requirements has become a necessity. In automotive applications, this necessity is more pronounced because of the safety regulations imposed by authorities. Semi-formal representation is an approach that helps making the requirements more understandable and rigorous. In particular, SysML has proved to have the capabilities to represent requirements, structure and behaviour of systems and devices in a diagram-based fashion, enabling the linking different elements that define the composition and the functionalities of the desired product. While for software systems and digital hardware it has been applied successfully, very little work has yet been done for analogue and analogue-mixed signal devices. This is mainly because of the particular behaviour of such devices and the continuous quantities related to them. In this paper, we describe the modelling of requirements for an electronic power switch in SysML. We show that the description of the requirements for analogue devices is possible and emphasize its utility in a real scenario.

Automotive power micro-electronic devices in the past were low pin-count, low complexity devices. Robustness could be assessed by stressing the few operating conditions and by manual analysis of the simple analog circuitry. Nowadays complexity of Automotive Smart Power Devices is driven by the demands for energy efficiency and safety, which adds the need for additional monitoring circuitry, redundancy, power-modes, leading even to complex System-on-chips with embedded uC cores, embedded memory, sensors and other elements. Assessing the application robustness of this type of microelectronic devices goes hand-in-hand with exploring their verification space inside and to certain extends outside of the specification. While there are well established methods for standard functional verification, methods for application oriented robust verification are not yet available. In this paper we present promising directions and first results, to explore and assess device robustness through various pre- and post-Si verification and design exploration strategies, focusing on metamodeling, constrained-random verification and hardware-in-the-loop experiments, for exploration of the operating space.

Simulation-based verification of electronic control units must face demands related to more functionality and less time to verify it. To ensure a reliable system, one must determine how the omnipresent, internal and external variations affect the target response, and find safe bounds for it. The main challenge is to optimally characterize a high number of sources of variation, with a reduced number of simulation runs. The paper conducts more efficient sensitivity and worst-case studies by applying concepts of Design of Experiments: screening to reduce the dimension of the verification space; sequential experiments for sensitivity analysis; gradient-based search for response bounds. The approach is evaluated on simulations of an airbag driver IC and compared with alternative methods.

The paper gives an overview on disk drive technology and how it determines the characteristics of the related electronics. Moreover, it details the resulting design methodology with an emphasis on system modeling and simulation. For instance, it is shown how key system properties, e.g. the seek time, can be determined through mixed simulation of mechanics, electronics and firmware. In addition, the same simulation environment is used to realistically verify analog and digital circuitry as well as software.

We present a new approach to circuit comparison which was developed to combine general applicability with most of the advantages of hierarchical processing. The basic principle of operation is the pattern matching of arbitrary subcircuits in larger circuits. Typically, a hierarchical schematic has to be compared with a flat netlist extracted from the layout. In our approach, this is accomplished by successive, bottom-up matching of schematic cells in the layout netlist, thus reconstructing the schematic hierarchy. The method is independent of circuit technology and design style. A sophisticated hierarchy handling scheme enables the usage of ill-structured schematic hierarchies. The typical problems in circuit comparison are overcome in a quite natural way by pattern matching. Real-life examples indicate the tool's suitability in function and performance. The hybrid approach is a mixture between the pattern matching approach and the traditional refinement technique. In this way, the advantages of both methods can be exploited.>

The authors present a novel approach to circuit comparison and building-block recognition. In contrast to conventional systems, netlist pattern matching is employed as the basic principle, making it possible to identify arbitrary subcircuits in larger circuits. Typically, a hierarchical netlist derived from a schematic and a flat netlist extracted from a layout have to be compared. In the present approach, this is accomplished by the successive (bottom up) matching of the schematic cells in the layout netlist, thus restoring the schematic hierarchy. The pattern matching algorithm is embedded in a sophisticated hierarchy handling scheme, making it possible to process even ill-structured hierarchies. The method is independent of circuit technology and design style. Typical drawbacks of traditional systems such as the handling of parallel paths or the permutability of (groups of) terminals are overcome in a quite natural way. Additionally, the proposed approach offers a universal and flexible solution to the problem of functional but not too topological isomorphic subcircuits. Real-life examples prove its suitability in function and performance.>