This article shows how to properly define modulated flicker noise in Verilog-A compact models, and how a simulator should handle flicker noise for periodic and transient analyses. By considering flicker noise in a simple linear resistor driven by a sinusoidal source, we demonstrate that the absolute value formulation used in most existing Verilog-A flicker noise models is incorrect when the bias applied to the resistor changes sign. Our new method for definition overcomes this problem, in the resistor as well as more sophisticated devices. The generalization of our approach should be adopted for flicker noise, replacing the formulation in existing Verilog-A device models, and it should be used in all new models. Since Verilog-A is the de facto standard language for compact modeling, it is critical that model developers use the correct formulation.

Just as digital design did 15 years ago; analog design has now reached a transition. The move to CMOS has made analog circuits more functionally complex, and that complexity leads naturally to functional errors in the designs, which in turn leads to respins and delays. And just as digital designers did 15 years ago, analog designers are beginning to realize that they need to employ a rigorous functional verification methodology.

Over the past 20 years, EDA has developed a solid digital implementation methodology that combines some restrictions on the design style with a set of comprehensive tools leading to predictable design flows. The recent increased use of analog components in complex SOC designs triggered a set of verification challenges ranging from simple connectivity problems to complex interferences between analog and digital data blocks. This panel discusses the state of the affairs in analog-mixed signal verification and draws a picture of future directions in terms of new approaches and tools.

Meeting performance specifications in the design of analog and RF (A/RF) blocks and integrated circuits (IC) continues to require a high degree of skill, creativity, and expertise. However, today's A/RF designers are increasingly faced with a new challenge. Functional complexity in terms modes of operation, extensive digital calibration, and architectural algorithms is now overwhelming traditional A/RF design methodologies. Functionally verifying A/RF designs is a daunting task requiring a rigorous methodology. As occurred in digital design, analog verification is becoming a separate and critical task. This paper describes the verification issues faced by the A/RF designer and presents a verification methodology to address these challenges. It presents a systematic approach to A/RF verification, the concept of an analog verification engineer, how to establish the methodology, and concludes with an example

Designers of RF circuits such as power amplifiers, mixers, and filters make extensive use of simulation tools which perform periodic steady-state analysis and its extensions, but until the mid 1990s, the computational costs of these simulation tools restricted designers from simulating the behavior of complete RF subsystems. The introduction of fast matrix-implicit iterative algorithms completely changed this situation, and extensions of these fast methods are providing tools which can perform periodic, quasi-periodic, and periodic noise analysis of circuits with thousands of devices. Even though there are a number of research groups continuing to develop extensions of matrix-implicit methods, there is still no compact characterization which introduces the novice researcher to the fundamental issues. In this paper, we examine the basic periodic steady-state problem and provide both examples and linear algebra abstractions to demonstrate connections between seemingly dissimilar methods and to try to provide a more general framework for fast methods than the standard time-versus-frequency domain characterization of finite-difference, basis-collocation, and shooting methods

Despite the fact that more and more electronic design is comprised of analog and mixed signal content, the design flows and methodologies in this area are lagging behind the pace of innovation in digital design. For sure, analog designers are in shorter supply, but this only makes the need for improvements and efficiency that much greater. Only of late have we seen production-worth attempts at functions such as analog synthesis and optimization reach the market. What is needed in today's analog design flow? What are the key technologies that are missing? How does the existing “food chain” need to work together to drive greater efficiencies?

The electronics industry is increasingly focused on the consumer marketplace, which requires low-cost high-volume products to be developed very rapidly. This, combined with advances in deep submicrometer technology have resulted in the ability and the need to put entire systems on a single chip. As more of the system is included on a single chip, it is increasingly likely that the chip will contain both analog and digital sections. Developing these mixed-signal (MS) systems-on-chip presents enormous challenges both to the designers of the chips and to the developers of the computer-aided design (CAD) systems that are used during the design process. This paper presents many of the issues that act to complicate the development of large single-chip MS systems and how CAD systems are expected to develop to overcome these issues.

We have simulated the phase noise of a voltage controlled oscillator (VCO) using an RF circuit simulator, SpectreRF/sup TM/. This simulator uses a variation of the periodic noise analysis first proposed by Okumura, et al (1993). It computes the power spectral density of the noise as a function of frequency. By assuming that only white noise sources are present in the oscillator, it is possible to derive a simple relationship between the level of the phase noise and the jitter. This excludes flicker noise from consideration, however, since flicker noise is a low-frequency phenomenon, excluding it only affects the accuracy of the long-term jitter. We compared the jitter with measurement and found the error to be less than 2 dB. An AHDL model for the VCO that efficiently exhibits jitter in the time domain is included. The model was written in Verilog-A. This model can be used to determine the affect of VCO jitter on a larger system, such as a phase-locked loop (PLL).

Design of communications circuits often requires computing steady-state responses to multiple periodic inputs of differing frequencies.Mixed frequency-time (MFT) approaches are orders of magnitude more efficient than transient circuit simulation, and perform better on highly nonlinear problems than traditional algorithms such as harmonic balance.We present algorithms for solving the huge nonlinear equation systems the MFT approach generates from practical circuits.

ing with credit is permitted. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from Publications Dept, ACM Inc., fax +1 (212) 869-0481, or [email protected]. 0-89791-847-9/97/0006/$3.50 hfill DAC 97 - 06/97 Anaheim, CA, USA Lumped Interconnect Models Via Gaussian Quadrature Keith Nabors, Tze-Ting Fang, Hung-Wen Chang and Kenneth S. Kundert Cadence Design Systems, San Jose, California Jacob K. White Massachusetts Institute of Technology, Cambridge, Massachusetts Abstract This paper presents a new Gaussian quadrature method for interconnect modeling which applies to one-dimensional distributions of circuit elementvalues, the line structures often used to model interconnect wires. The method takes a line circuit, whichmay be an arbitrary combination of lumped and distributed elements, and produces a small lumped model whose transfer and input characteristics approximately mat...

In this paper we present a preconditioned recycled Krylov-subspace method to accelerate a recently developed approach for AC and noise analysis of linear periodically-varying communication circuits. Examples are given to show that the combined method can be used to analyze switching filter frequency response, mixer 1/f noise frequency translation, and amplifier intermodulation distortion. In addition, it is shown that for large circuits the pre-conditioned recycled Krylov-subspace method is up to forty times faster than the standard optimized direct methods.

Gaussian-elimination based shooting-Newton methods, a commonly used approach for computing steady-state solutions, grow in computational complexity like N 3 , where N is the number of circuit equations.Just using iterative methods to solve the shooting-Newton equations results in an algorithm which is still order N 2 because of the cost of calculating the dense sensitivity matrix.Below, a matrix-free Krylov-subspace approach is presented, and the method is shown to reduce shooting-Newton computational complexity to that of ordinary transient analysis.Results from several examples are given to demonstrate that the matrix-free approach is more than ten times faster than using iterative methods alone for circuits with as few as 400 equations.2 Shooting Methods Finding the periodic steady-state solution of a circuit involves nding the initial condition for the circuit's associated system of dierential equations such that the solution at the end of the period matches the initial condition.More precisely, nding the steady-state solution means nding a particular solution to the circuit equations, as

A procedure for modeling and simulation of arbitrary nonlinear magnetics devices is presented. A set of electromagnetic primitives is described as implemented in SpectreHDL. The primitives include cores, gaps, and windings that are combined to model ferromagnetic inductors and transformers. A ferromagnetic core model based on the Jiles/Atherton algorithm [1986] is described. The model is used to illustrate how to overcome some difficult modelling issues such as hysteresis, implicit equations, and multi-disciplinary models.

In this paper we describe an algorithm for ecient circuit-level simulation of transmission lines which can be speci ed by tables of frequency-dependent scattering parameters.The approach uses a forced stable section-by-section `2 minimization approach to construct a high order rational function approximation to the frequency domain data, and then applies guaranteed stable balanced realization techniques to reduce the order of the rational function.The rational function is then incorporated in a circuit simulator using fast recursive convolution.An example of a transmission line with skin-eect is examined to both demonstrate the eectiveness of the approach and to show its generality. 31

The transient behavior of circuits like switching power converters and switched capacitor filters are expensive to simulate because they are clocked at a frequency whose period is orders of magnitude smaller than the time interval of interest to the designer. It is possible to reduce the simulation time without compromising accuracy by exploiting the fact that the behavior of such a circuit in a given high-frequency clock cycle is similar, but not identical, to its behavior in the preceding and following cycles. In particular, the envelope of the high-frequency clock can be followed by accurately computing the circuit behavior over occasional cycles. The authors describe the implementation of an envelope-following method that is particularly efficient for switching power and filter circuits, and they present results demonstrating the method's effectiveness.>

Simulation in the frequency domain avoids many of the severe problems experienced when trying to use traditional time-domain simulators such as SPICE to find the steady-state behavior of analog and microwave circuits. In particular, frequency-domain simulation eliminates problems from distributed components and high-Q circuits by foregoing a nonlinear differential equation representation of the circuit in favor of a complex algebraic representation. This paper reviews the method of harmonic balance as a general approach to converting a set of differential equations into a nonlinear algebraic system of equations that can be solved for the periodic steady-state solution of the original differential equations. Three different techniques are applied to solve the algebraic system of equations: optimization, relaxation, and Newton's method. The implementation of the algorithm resulting from the combination of Newton's method with harmonic balance is described. Several new ways of exploiting both the structure of the formulation and the characteristics of the circuits that would typically be seen by this type of simulator are presented. These techniques dramatically reduce the time required for a simulation, and allow harmonic balance to be applied to much larger circuits than were previously attempted, making it suitable for use on monolithic microwave integrated circuits (MMIC's).