This paper demonstrates a 12-bit 100-MS/s PVT-stabilized pipelined-SAR ADC with fully integrated on-chip calibration. Two key innovations facilitate over 65-dB SNDR with less than 2.2-dB variation from -20 °C to 125 °C: First, a PVT-stabilized nested negative-C topology boosts open-loop gain ($G_{ol}$) of the residue amplifier (RA) by 28 dB, enabling one-time foreground calibration that avoids persistent inter-stage gain error tracking. Second, a dynamic auto-zeroing technique addresses offsets from both the RA and first-stage comparator through a switched-capacitor filter that extracts offsets based on the stochastic characteristics of residue signals. Dynamically level-shifted capacitors (DLSC) are embedded at the differential inputs to neutralize aliased noise and thermal noise, so that the offset drifts under high-temperature environment are effectively cancelled. Fabricated in 40-nm CMOS, the prototype occupies 0.22 mm2and achieves 65.5-dB SNDR and 83-dB SFDR at Nyquist input while consuming 3.7 mW. Across six tested chips, the prototype design exhibits merely 2.2-dB SNDR degradation over -20 °C ~ 125 °C and 1.3-dB variation under ± 5 % supply voltage (1.1 V) fluctuations.

This article presents a 5-GS/s 8-bit single-channel hybrid analog-to-digital converter (ADC) with a$\lambda $/4 transmission line (T-Line) based time-to-digital converter (TDC). Taking advantage of the traveling wave technique, the T-Line based TDC breaks the time step (TLSB) limitation caused by jitter tolerance and process, voltage, and temperature (PVT) variations. An improved bootstrapped generator for the input switch enables rapid start-up and reduces tracking time, accommodating the high sampling rate. Fabricated in a 28-nm CMOS technology, the prototype ADC core consumes 19.8 mW at 5 GS/s with a 0.9-V supply. It achieves a signal-to-noise and distortion ratio (SNDR) of 38.04 dB with a Nyquist input, corresponding to a Walden figure-of-merit of 60.7 fJ/conv-step. The measured variation in SNDR is below 0.34 dB across temperature variation of$- 25~^{\circ }$C to$125~^{\circ }$C, and below 0.74 dB over supply variations of ±5%.

This brief presents an on-chip, real-time rotation calibration (RRC) technique aimed at alleviating the inter-channel offset mismatch in time-interleaved (TI) successive-approximation register analog-to-digital converter (SAR ADC). By leveraging auto-rotation calibration and self-compensation strategies in the analog domain, the proposed technique demonstrates robust performance across PVT variations. Two additional sub-channels are involved in the TI quantization mechanism, where the continuous rotation of the sampling clock distribution ensures their operation in calibration mode. To validate the effectiveness of the proposed calibration, an$8\times 8$bit 8 GS/s TI-SAR ADC is designed and implemented in a 28-nm process and occupies an active area of 0.273 mm2, with each sub-channel SAR ADC covering only$86\times 23~\mu $m. Extensive simulation results validate the efficacy of RRC, demonstrating significant improvements in dynamic performance. Specifically, SNDR increases from 37.1 to 45.4 dB, while SFDR rises from 57.8 to 60.7 dB, as observed at the Nyquist input frequency.

This paper introduces a dual main clock generator (DMCG) and a digital serializer (DS) to improve the power efficiency of the time-interleaving (TI) analog-to-digital converters (ADCs). The proposed DMCG combines a dual-path front end and an improved selecting signal generator that addresses the potential phase error and reduces the peak current of the clock-driving circuits by 60%. The DS is proposed to serialize the digital outputs without employing power-hungry inverter-based buffer chains thus reducing the power consumption by 39.2%. The reference-free time skew extraction algorithm (RFA) is presented to mitigate the accuracy deterioration due to selecting the fixed middle channel. These techniques are validated by a prototype 12-bit 10-GS/s TI pipelined successive approximation register (TI-Pi-SAR) ADC. Fabricated in a 28-nm CMOS process, the prototype chip occupies an area of 4.4 mm2. The measurement results show that the ADC achieves a 49.8 dB SNDR and 60.0 dB SFDR after calibration at Nyquist frequency, while the total power consumption is 270 mW, leading to the figure of merits of Schreier (FoM$_{\mathrm {S}}$) and Walden (FoM$_{\mathrm {W}}$) of 152.5 dB and 106.9 fJ/conv.-step, respectively.

This article presents a low supply voltage and low-power charge-pump phase-locked loop (CPPLL) with phase noise (PN) improvement and reference spur reduction techniques. The$V_{\mathrm {ref}}$adaptive adjustment mechanism is analyzed in the class-C voltage-controlled oscillator (VCO) with dual-mixed loops, which eliminates the PN’s sensitivity to temperature and process. Moreover, based on resistance-based accurate current replication, the low-power and low-current mismatch charge-pump (CP) circuit structure is proposed to reduce the reference spur of the PLL. In addition, by using the dynamic current compensation scheme, the power consumption of the CP is greatly reduced. The proposed PLL is fabricated in a 0.18-$\mu \text{m}$RF CMOS process with an area of 1.07$\times $1.07 mm2. The measurement results show that the proposed PLL achieves a 2.24–2.85-GHz frequency tuning range and a PN of −123.97 dBc/Hz at 1-MHz offset from a 2.55-GHz carrier. The measured reference spur is −89.4 dBc at 40-MHz offset frequency and the total power consumption is 2.62 mW at the 0.8-V power supply voltage.

In run-time safety analysis the executions of a concurrent program are monitored and analyzed with respect to safety properties. Similar to testing, run-time analysis is quite efficient, but it also tends to be incomplete. The results pertain only to the observed executions which may constitute just a small subset of all possible executions.