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Harsha Sathyamurthy

dblp:65/2536 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 75% Processor architecture and microarchitecture · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › clock network synthesis
clock skew optimization		 0.011998
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Electronic design automation › physical design
gate sizing		 0.011998
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Processor architecture and microarchitecture › pipelining
pipelined circuits		 0.011998
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Electronic design automation › physical design
timing optimization		 0.011998
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998

Methods — techniques the papers use, named apart from their topics

timing analysis · 0.0sensitivity-based optimization · 0.0
YearPublicationVenuePosition
1998 Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization
abstract
An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure described herein utilizes the idea of cycle borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. The theoretical basis for the procedure is developed, a new algorithm for timing analysis of acyclic pipeline circuits with deliberate skew is presented, and a sensitivity-based optimizer is used to solve the sizing+skew problem. Our experimental results verify that the procedure of cycle borrowing using sizing+skew results in a better overall area-delay tradeoff as compared to using sizing alone.
Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1995 Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization
abstract
An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.
Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn
 ICCAD1