Bob Boothe

dblp:65/2913 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Debugging and program repair · 100%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 65% Parallel and multicore computing · 22% High-performance computing · 7%
Computer networks
1 paper
Network performance modeling · 100%

Topics — the 8 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Debugging and program repair
reverse execution
0.012000
Efficient algorithms for bidirectional debugging · PLDI 2000
Network performance modeling
bandwidth-constrained networks
0.011993
Performance on a Bandwidth Constrained Network: How much bandwidth do we need? · SC 1993
Network performance modeling
bandwidth requirements
0.011993
Performance on a Bandwidth Constrained Network: How much bandwidth do we need? · SC 1993
Processor architecture and microarchitecture
latency hiding
0.011992
Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessors · ISCA 1992
Processor architecture and microarchitecture
memory latency tolerance
0.011992
Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessors · ISCA 1992
Processor architecture and microarchitecture
multithreading
0.011992
Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessors · ISCA 1992
Parallel and multicore computing › multiprocessor system
shared-memory multiprocessor
0.011992
Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessors · ISCA 1992
Memory systems
cache coherence
0.011992
Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessors · ISCA 1992

Methods — techniques the papers use, named apart from their topics

replay · 0.0checkpointing · 0.0context switching · 0.0compiler optimization · 0.0
YearPublicationVenuePosition
2000 Efficient algorithms for bidirectional debugging
abstract
This paper discusses our research into algorithms for creating an efficient bidirectional debugger in which all traditional forward movement commands can be performed with equal ease in the reverse direction. We expect that adding these backwards movement capabilities to a debugger will greatly increase its efficacy as a programming tool.
Bob Boothe
PLDI1
1993 Performance on a Bandwidth Constrained Network: How much bandwidth do we need?
Bob Boothe, Abhiram G. Ranade
SC1
1992 Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessors
abstract
Shared memory multiprocessors are considered among the easiest parallel computers to program. However building shared memory machines with thousands of processors has proved difficult because of the inevitably long memory latencies. Much previous research has focused on cache coherency techniques, but it remains unclear if caches can obtain sufficiently high hit rates. In this paper we present improved multithreading techniques that can easily tolerate latencies of hundreds of cycles, and yet only require a small number of threads per processor. High performance is achieved by introducing an explicit context switch instruction that can be used by a simple optimizing compiler to group together several shared accesses. This grouping of shared accesses dramatically reduces the frequency of context switches compared to simpler multithreading models. The combination of our techniques achieves efficiencies of 80% or higher on a broad set of applications.
Bob Boothe, Abhiram G. Ranade
ISCA1