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Thomas Zaremba

dblp:65/3296 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › special-purpose processor
direct execution architecture		 0.011987
An Architecture for the Direct Execution of the Forth Programming Language · ASPLOS 1987
Processor architecture and microarchitecture
instruction set architecture		 0.011987
An Architecture for the Direct Execution of the Forth Programming Language · ASPLOS 1987
Processor architecture and microarchitecture › instruction set architecture › instruction set style
stack architecture		 0.011987
An Architecture for the Direct Execution of the Forth Programming Language · ASPLOS 1987
YearPublicationVenuePosition
1987 An Architecture for the Direct Execution of the Forth Programming Language
abstract
We have developed a simple direct execution architecture for a 32 bit Forth microprocessor. The processor can directly access a linear address space of over 4 gigawords. Two instruction types are defined; a subroutine call, and a user defined microcode instruction. On-chip stack caches allow most Forth primitives to execute in a single cycle.
John R. Hayes, Martin E. Fraeman, Robert L. Williams, Thomas Zaremba
 ASPLOS4