This correspondence points out some of the problems with Weiser's algorithm [5] for computing program slices. Corrections are made to Weiser's algorithm. It is shown how Weiser's algorithm can be amended to handle loops. Advantages of the Bergeretti and Carre's approach [1] are discussed.

Engineers use large amounts of stereotype knowledge about basic circuit components and design techniques when designing a circuit. This knowledge is used to guide design decisions in order to produce an optimal design. Such stereotyped knowledge can be represented as frames in a knowledge based system and such a knowledge base can be used to implement a silicon compiler. This paper describes a pilot system we are developing at SFU which uses frames to represent abstract models of circuit components. Filling in the slots of the frame results in the refinement of an abstract model into a layout. The pilot system will design storage structures such as static RAMs and registers using standard cells. With the experience we gain from this pilot system we plan to develop a knowledge base system which can translate a register transfer level description of a circuit into a layout of acceptable quality.

This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM's, and MUX's. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.

This paper presents low-level architectural features for supporting software systems which are organized as collections of concurrent processes in which processes may be created or destroyed and interprocess interaction paths may be established and closed over the course of system's operation. The interprocess interaction aspect of the mentioned systems is discussed in some detail and a suitable architecture is developed for a processor which provides for efficient coordination and communication between processes running on possibly different computers.

Various possible implementation schemes for concurrent programming concepts are surveyed. Based upon this examination, computer design features are proposed which assist in the efficient realization of concurrent programming concepts in a multiprocessor machine which is constructed from a number of self-contained processors, each with its own random access memory. It is indicated how the proposed architecture provides hardware support for creating and terminating parallel execution paths. The hardware supports scheduled sharing of resources as its basic design feature. In particular, the problem of implementing scheduled waits in monitors is examined in detail. This is done in an environment where processes distributed among several physical processors are using a common monitor. It is also shown how the practical aspects of error resynchronization can be handled efficiently.