Demo Data from EDBT 2026 / reviewers in the wild / expert
Keijiro Nakamura
dblp:65/3612
· DBLP profile ↗
4ranked-venue papers
3as first author
0since 2021 · last 2020
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-authorApplied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 92% Integrated circuit design · 8% | |
| Theoretical computer science
1 paper |
Computational complexity · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 3 | 1987 | Inverter-Minimum Networks · IEEE Trans. Computers 1987 Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks · IEEE Trans. Computers 1979 Minimal Negative Gate Networks · IEEE Trans. Computers 1972 |
Electronic design automation › logic synthesis › logic optimization
inverter minimization |
0.0 | 1 | 1987 | Inverter-Minimum Networks · IEEE Trans. Computers 1987 |
Computational complexity › circuit complexity › boolean circuits
inversion complexity |
0.0 | 1 | 1987 | Inverter-Minimum Networks · IEEE Trans. Computers 1987 |
Electronic design automation › logic synthesis › circuit optimization
gate-count minimization |
0.0 | 1 | 1972 | Minimal Negative Gate Networks · IEEE Trans. Computers 1972 |
Integrated circuit design › digital circuit design
logic design |
0.0 | 1 | 1972 | Minimal Negative Gate Networks · IEEE Trans. Computers 1972 |
Integrated circuit design › large-scale integration
MOS LSI |
0.0 | 1 | 1979 | Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks · IEEE Trans. Computers 1979 |
Methods — techniques the papers use, named apart from their topics
feed-forward network analysis · 0.0negative gate logic · 0.0monotone function decomposition · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Effects of Myocardial Fat's Thickness and Myocardial Impedance on Bipolar Radiofrequency Cathode AblationabstractRadiofrequency cathode ablation is an effective tool for the treatment of cardiac arrhythmia. Bipolar ablation may provide a more localized lesion and therefore prevent side effects and complications caused by cathode ablation. However, myocardial impedance and heart fat's thickness may have significant influence on the performance of bipolar ablation. In this study, we perform computer simulation to study the influence of myocardial impedance and heart fat's thickness on bipolar and unipolar cathode ablation. Through computer simulation, we obtain and compare the treatment effects under different configurations of cathode ablation. The simulation results are generally consistent with experiment results. Through our simulation, when the fat layer's thickness increases, the bipolar ablation's heating effect decreases, but the final ablation effect is still better than that of unipolar ablation. The ablation performance is improved when myocardial impedance decreases. However, the heating effect of the bipolar configuration is more sensitive to the variation of myocardial impedance and fat layers' thickness compared with that of the unipolar configuration. Xin Zhu 0001, Keijiro Nakamura |
TENCON | 3 |
| 1987 | Inverter-Minimum NetworksabstractLet Fm= (f1,...,fm) be a vector of m logical functions. Let Inv (Fm), the inversion complexity of Fm, be the minimum number of inverters required to realize Fm by a feed-forward network using AND gates, OR gates, and inverters. Keijiro Nakamura |
IEEE Trans. Computers | 1 |
| 1979 | Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate NetworksabstractA negative gate is a gate which can realize an arbitrary negative function. The problem of synthesizing logical networks, with negative gates only, is important for the design of MOS LSI. Keijiro Nakamura |
IEEE Trans. Computers | 1 |
| 1972 | Minimal Negative Gate NetworksabstractA negative gate is a gate that can realize an arbitrary negative function (or monotone decreasing function) and a positive gate is one that can realize an arbitrary positive function (or monotone increasing function). This paper discusses methods of realizing a given logical function or a given set of logical functions using a minimum number of negative gates alone or using a minimum number of negative and positive gates. Keijiro Nakamura, Nobuki Tokura, Tadao Kasami |
IEEE Trans. Computers | 1 |