Traditional standard cell libraries employ a single-input switching (SIS) assumption for characterization. However, in real circuits, multiple inputs can switch simultaneously, resulting in a significant speed-up. This discrepancy can lead to circuit failures due to inaccurate early analysis, despite static timing analysis (STA) tools adopting conservative strategies. Consequently, multi-input switching (MIS) models have gained importance for timing libraries. For complex logic gates, however, the number of possible transitions that must be considered for characterization increases significantly, posing a substantial challenge in modeling MIS effects. We propose a novel approach to address this challenge by combining the power of satisfiability (SAT) solvers and machine learning (ML) techniques. First, we perform a logical analysis on the Boolean function of a given logic gate to identify input patterns that can lead to MIS-induced speed-up. This task is formulated as a SAT problem, and a SAT solver is utilized to extract all MIS-relevant transitions, thereby significantly reducing the characterization and modeling effort. Next, we leverage ML techniques to accurately capture the complex dependencies of MIS-induced speed-up under various circuit and environmental conditions. To streamline this process, we introduce an automated tool framework named LiMo (Library Model), which integrates a SAT solver, SPICE simulator, dataset optimization strategies, ML training/testing infrastructure, and multiprocessing capabilities to create MIS-aware timing libraries. The results on benchmark circuits reveal that ignoring MIS effects can result in relative root mean square errors (RRMSE) exceeding 40% in timing attributes. In contrast, LiMo-generated libraries achieve RRMSE errors below 7% compared to SPICE simulations, while delivering results$\sim 10,000 \times $faster, underscoring their suitability for incorporating MIS effects in STA for industrial designs.

We propose switching activity factor-based effective current source model (SAFE) for aging-aware static timing analysis (STA), a new technique for estimating the timing performance of digital circuits. SAFE is based on the development of device-level variation-aware analytical timing models of stacked and multistage logic cells (commonly employed transistor topologies in a synthesized netlist of a random logic path), which drastically reduces the recharacterization efforts of the standard cells. The models developed are derived as a function of input transition time$(T_{R})$and load capacitance$(C_{L})$. The timing performance of a standard cell degrades with threshold voltage$(V_{\mathrm {th}})$degradation in a MOS device due to various aging mechanisms. SAFE, makes the entire STA process aging aware by updating its model coefficients with$V_{\mathrm {th}}$degradation caused by aging. It is achieved by proposing a method for estimating$V_{\mathrm {th}}$degradation under various stress conditions, including static, dynamic, and asymmetric, that applies to any process design kit (PDK). To consider asymmetric aging, we have developed a method to find effective switching activity factor$(\alpha _{\mathrm {eff}})$for N-stage stacked and N-stage parallel logic which is used to find the value of switching activity factor$(\alpha)$at intermediate nodes in pipelined logic circuits. Our simulations are performed in Mentor Graphics Eldo SPICE environment using STMicroelectronics 28 and 65-nm CMOS process. The proposed technique provides a high-simulation accuracy (2.5% average error) when compared with SPICE simulations. Finally, we achieved a ~98.14% reduction in the required number of simulations using SAFE when compared with a completely SPICE/Aging simulation-based approach.

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage$(V_{\mathrm{ th}})$of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time ($t$). A device-level approach for$V_{\mathrm{ th}}$degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of$t$. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with$t$to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.

We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the population. This uses considerably less memory compared to a method with direct position-encoding for members of the population. The algorithm has been implemented in C++, and the results on MCNC benchmark circuits are presented. The results are superior to those obtained using conventional Simulated Annealing (SA) based approach. The results of an EP-SA approach using the proposed evolutionary programming method are also presented.