Learning an assembly language introduces students to important computing concepts such as the program stack and lays the conceptual groundwork for topics such as caching. While many instructors choose a RISC language such as MIPS for teaching assembly languages, the pervasiveness of x86-64 in both the desktop and server environments has compelled many instructors to adopt it in their courses. Unfortunately, x86-64 is a complex assembly language and as a result students often have difficulty understanding and visualizing the execution of an x86-64 program. This is especially the case for introductory level students, who struggle with the concepts of control flow; the difference between registers and memory; and memory organization (e.g. the stack).

Numerous studies have demonstrated the effectiveness of flipped classrooms (e.g. peer instruction) in computer science courses. Flipped classrooms rely on students having obtained first exposure to concepts through pre-class activities such as viewing videos or reading a textbook. Having engaged with the material before class, class time can be spent on more challenging activities with feedback from the instructor and classmates. These pre-class activities can be a challenge for students, who often do not have the skills necessary to critically engage with the assigned reading/viewing. As a result students often come to class under-prepared despite completing the pre-class activities. This paper presents the author's experience with adding guided practice worksheets to improve student preparedness in two courses: a CS1 course and a lower-division "Introduction to Computer Systems" course. These pre-class worksheets provided a structured set of learning objectives for students to focus on in their reading as well as exercises to test those objectives. Limited results indicate a high worksheet completion rate and a strong positive correlation between individual completion rates and final course grade. This paper also presents recommendations for those instructors wishing to adopt guided practice in their class.

Meaningful and engaging assignments are important to retention in CS. An interesting problem context may be able to make routine practice of programming basics more interesting for students. Problem contexts also provide the opportunity to bring in content related to social justice topics, which are important for providing students a well-rounded education. With funding from the NSF (#1339404), we have developed eight homework assignments that integrate social justice topics as the problem context for CS1 assignments. Workshop attendees will work in small groups to revise or adapt existing assignments, translate existing assignments into the language of their course, or develop a new assignment. Attendees will be encouraged to submit their work to Nifty Assignments for 2019 and NCWIT's peer-reviewed curriculum repository, Engage CS Edu (engage-csedu.org). All assignments will be posted on CSTeachingTips.org to be shared with the community.

Research shows the benefit of using active learning in computer science education; however, only limited resources (such as, prior publications) exist for systems courses (including architecture, networking, operating systems). This BoF brings together practitioners of various levels of experience to discuss ways to augment or replace traditional lecturing. We will discuss different techniques, possible materials available, and results measured. This BoF should benefit both instructors considering adopting techniques and instructors looking to discuss issues with their usage.

Process-Oriented Guided Inquiry Learning (POGIL) is a research-based instructional strategy with a proven history across STEM disciplines. In a POGIL classroom, teams of students work on activities that are specifically designed to guide them to construct their own understanding of key concepts. At the same time, students develop process skills such as communication, teamwork, problem solving, and critical thinking. POGIL incorporates practices shown to be particularly helpful for students from underrepresented populations. In a POGIL classroom, teachers are facilitators, not lecturers. Multiple studies have shown that students in POGIL classes do better on common exams and in subsequent courses. For more information, see http://cspogil.org and http://pogil.org. This BOF will (1) enable people unfamiliar with POGIL to ask questions and learn more, and (2) bring together experienced POGIL practitioners to share experiences, concerns, ideas, and insights. As in a POGIL classroom, we will discuss topics in small teams and report out to the larger group.

Process-Oriented Guided Inquiry Learning (POGIL) is a research-based instructional strategy with a proven history across STEM disciplines. In a POGIL classroom, teams of students work on activities that are specifically designed to guide them to construct their own understanding of key concepts. At the same time, students develop process skills such as communication, teamwork, problem solving, and critical thinking. POGIL incorporates practices shown to be particularly helpful for students from underrepresented populations. In a POGIL classroom, teachers are facilitators, not lecturers. Multiple studies have shown that students in POGIL classes do better on common exams and in subsequent courses. For more information, see http://cspogil.org and http://pogil.org. This BOF will (1) enable people unfamiliar with POGIL to ask questions and learn more, and (2) bring together experienced POGIL practitioners to share experiences, concerns, ideas, and insights. As in a POGIL classroom, we will discuss topics in small teams and report out to the larger group.

Shadow memory is a critical component of many dynamic program analysis frameworks with applications ranging from memory debugging to computer security. Most recent work has focused on optimizing the execution time of analyses that associate a single tag with each memory address. However, an important new class of dynamic analyses (poly-scopic analyses) requires multiple tags for each memory address. These new analyses place additional burdens on memory shadowing infrastructures, especially with regards to memory overhead. Existing shadow memory infrastructures are either unequipped to handle these additional burdens or result in runtime and memory overheads that make them impractical for all but small inputs. In this paper we propose vector shadow memories (VSMs) as an infrastructure to support poly-scopic analyses. Furthermore we introduce Skadu, a VSM implementation that employs several novel techniques to greatly reduce the runtime and memory overhead associated with the two major challenges of VSMs: tag validation and garbage collection. Our results show that on two separate poly-scopic analyses, memory footprint profiling and hierarchical critical path analysis, Skadu significantly reduces the associated memory overhead: by 14.2× and 11.4× respectively. In both cases, Skadu makes poly-scopic analysis practical for ordinary desktop and laptop machines.

Peer Instruction (PI) has been shown to be successful at improving pass-rates and improving retention of majors in large classes at large research-intensive institutions. At these institutions, students have been shown to learn from peer discussion in PI and both students and faculty have reported that they value PI in their classrooms. However, little is known about the effectiveness of PI in small classrooms at teaching-focused liberal arts colleges. This study evaluates results from seven lower-division classes and four upper-division classes taught at three different liberal arts institutions using PI. In these classes, PI experienced similar success as that reported at large-research intensive universities, both in terms of student learning from peer discussion and from student attitudinal surveys. Most notably, of 137 surveyed students, 91% recommend more faculty use PI in their classes.

Many studies have demonstrated that students tend to learn less than instructors expect in CS1. In light of these studies, a natural question is: to what extent do these results hold for subsequent, upper-division computer science courses? In this paper we describe our work in creating high-level concept questions for an upper-division computer architecture course. The questions were designed and agreed upon by subject-matter and teaching experts to measure desired minimum proficiency of students post-course. These questions were administered to four separate computer architecture courses at two different institutions: a large public university and a small liberal arts college. Our results show that students in these courses were indeed not learning as much as the instructors expected, performing poorly overall: the per-question average was only 56%, with many questions showing no statistically significant improvement from pre-course to post-course. While these results follow the trend from CS1 courses, they are still somewhat surprising given that the courses studied were taught using research-based pedagogy that is known to be effective across the CS curriculum. We discuss implications of our findings and offer possible future directions of this work.

Peer Instruction (PI) is an active learning pedagogical technique. PI lectures present students with a series of multiple-choice questions, which they respond to both individually and in groups. PI has been widely successful in the physical sciences and, recently, has been successfully adopted by computer science instructors in lower-division, introductory courses. In this work, we challenge readers to consider PI for their upper-division courses as well. We present a PI curriculum for two upper-division computer science courses: Computer Architecture and Theory of Computation. These courses exemplify several perceived challenges to the adoption of PI in upper-division courses, including: exploration of abstract ideas, development of high-level judgment of engineering design trade-offs, and exercising advanced mathematical sophistication. This work includes selected course materials illustrating how these challenges are overcome, learning gains results comparing these upper-division courses with previous lower-division results in the literature, student attitudinal survey results (N = 501), and pragmatic advice to prospective developers and adopters. We present three main findings. First, we find that these upper-division courses achieved student learning gains equivalent to those reported in successful lower-division computing courses. Second, we find that student feedback for each class was overwhelmingly positive, with 88% of students recommending PI for use in other computer science classes. Third, we find that instructors adopting the materials introduced here were able to replicate the outcomes of the instructors who developed the materials in terms of student learning gains and student feedback.

Complex “fat operators” are important contributors to the efficiency of specialized hardware. This paper introduces two new techniques for constructing efficient fat operators featuring up to dozens of operations with arbitrary and irregular data and memory dependencies. These techniques focus on minimizing critical path length and load-use delay, which are key concerns for irregular computations. Selective Depipelining(SDP) is a pipelining technique that allows fat operators containing several, possibly dependent, memory operations. SDP allows memory requests to operate at a faster clock rate than the datapath, saving power in the datapath and improving memory performance. Cachelets are small, customized, distributed L0 caches embedded in the datapath to reduce load-use latency. We apply these techniques to Conservation Cores(c-cores) to produce coprocessors that accelerate irregular code regions while still providing superior energy efficiency. On average, these enhanced c-cores reduce EDP by 2× and area by 35% relative to c-cores. They are up to 2.5× faster than a general-purpose processor and reduce energy consumption by up to 8× for a variety of irregular applications including several SPECINT benchmarks.

Software engineers now face the difficult task of refactoring serial programs for parallel execution on multicore processors. Currently, they are offered little guidance as to how much benefit may come from this task, or how close they are to the best possible parallelization. This paper presents Kismet, a tool that creates parallel speedup estimates for unparallelized serial programs. Kismet differs from previous approaches in that it does not require any manual analysis or modification of the program. This difference allows quick analysis of many programs, avoiding wasted engineering effort on those that are fundamentally limited. To accomplish this task, Kismet builds upon the hierarchical critical path analysis (HCPA) technique, a recently developed dynamic analysis that localizes parallelism to each of the potentially nested regions in the target program. It then uses a parallel execution time model to compute an approximate upper bound for performance, modeling constraints that stem from both hardware parameters and internal program structure.

Many recent parallelization tools lower the barrier for parallelizing a program, but overlook one of the first questions that a programmer needs to answer: which parts of the program should I spend time parallelizing?

This paper overviews Kremlin, a software profiling tool designed to assist the parallelization of serial programs. Kremlin accepts a serial source code, profiles it, and provides a list of regions that should be considered in parallelization. Unlike a typical profiler, Kremlin profiles not only work but also parallelism, which is accomplished via a novel technique called hierarchical critical path analysis. Our evaluation demonstrates that Kremlin is highly effective, resulting in a parallelized program whose performance sometimes outperforms, and is mostly comparable to, manual parallelization. At the same time, Kremlin would require that the user parallelize significantly fewer regions of the program. Finally, a user study suggests Kremlin is effective in improving the productivity of programmers.

Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full speed at one time. In this regime, specialized, energy-efficient processors can increase parallelism by reducing the per-computation power requirements and allowing more computations to execute under the same power budget. To pursue this goal, this paper introduces conservation cores. Conservation cores, or c-cores, are specialized processors that focus on reducing energy and energy-delay instead of increasing performance. This focus on energy makes c-cores an excellent match for many applications that would be poor candidates for hardware acceleration (e.g., irregular integer codes). We present a toolchain for automatically synthesizing c-cores from application source code and demonstrate that they can significantly reduce energy and energy-delay for a wide range of applications. The c-cores support patching, a form of targeted reconfigurability, that allows them to adapt to new versions of the software they target. Our results show that conservation cores can reduce energy consumption by up to 16.0x for functions and by up to 2.1x for whole applications, while patching can extend the useful lifetime of individual c-cores to match that of conventional processors.

DNA self-assembly is emerging as the most promising technique for nanoscale self-assembly as it uses the simple, yet precise rules of DNA binding to create macroscale assemblies from nanoscale components. However, DNA self-assembly is also highly error-prone and requires the use of error-resilience techniques in order to unlock its potential. In this paper we propose a technique for error-resilience that is based on information redundancy but, in contrast to previous information redundancy schemes, can achieve much higher resilience to growth errors. By expanding the neighborhood from which redundant information is taken, we can extend the distance that errors are propagated and therefore increase the likelihood of the error being reversed. Given a growth error rate of ∈, we show that with a neighborhood of only 2 we can reduce the error rate to ∈3.64for arbitrary functions (as compared to ∈2.33previously achieved). Compared with spatial redundancy approaches, our technique allows for higher density nanostructures and has a greatly reduced assembly time.