Interconnect parasitics are playing a dominant role in determining chip performance and functionality in deep-submicron designs. This problem is compounded by increasing chip frequencies and design complexity. As parasitic coupling capacitances are a significant portion of total capacitance in deep-submicron designs, verification of both performance and functionality assumes greater importance. This paper describes techniques for the modeling and analysis of parasitic coupling effects for large VLSI designs. Analysis results from a controlled experimental setup are presented to show the need for accurate cell models. Results from application of these techniques on a lending edge Digital Signal Processor (DSP) design are presented. Accuracy comparison with detailed SPICE-level analysis is included.

A unified multilevel mixed-mode simulation capability for mixed analog/digital integrated circuits is described. First, a methodology for describing arbitrary analog or mixed analog/digital blocks at the behavioral level is proposed. In order to verify such models, a verification tool has been developed. The tools modgens and modgenz convert transfer functions H(s) and H(z), respectively, into state space representations in the time domain and generate behavioral models. Thus, the methodology allows digital, analog, and mixed analog/digital subcircuits to be described at various levels. While the analog portions of the circuit are simulated with high accuracy, the digital portions can be simulated in various models. Simulation is event-driven. For the behavioral analog models, block elimination with unique reordering and pivoting techniques are used to accommodate state variables. This capability has been integrated into the MOTIS3 design verification system. The simulation of representative mixed analog/digital simulation examples is described.>

Models and techniques used in a switched-capacitor functional model generator are described. The simulation models described are asynchronous with respect to the clock inputs, and the proposed models are useful for achieving functional verification of chips consisting of clock generating circuitry, switched-capacitor circuits, and other analog or digital blocks. Graph-based methods are used for each clock configuration to minimize CPU requirements. Continuous feedthrough of the analog signals is adequately handled. The program MODGENSC has been developed to generate the models directly from the circuit description in SWITCAP. With this capability, full-chip mixed digital/analog simulation is achievable and the simulation time is reduced significantly.>

The method presented allows digital, analog and mixed D/A portions of a circuit to be described at behavioral, functional, cell, and transistor levels. The analog portions of the circuit are simulated with maximum accuracy while the digital portions are simulated in various modes. M/sup 3/ is event-driven and uses block elimination with unique reordering and pivoting techniques to accommodate state variables for behavioral analog or mixed D/A models. The simulator has been integrated into the MOTIS3 design verification system. A representative mixed D/A simulation example is included.>

The simulator is built on the second-generation MOTIS mixed-mode simulator to accommodate simulation for analog circuits. It uses circuit-simulation techniques for the analog portions of the chip, and timing and logic simulation techniques for the digital portions. The simulator can be used for overall design verification of a chip at the transistor level.>

A nonlinear constrained optimizer, WATOPT, targeted towards circuit applications is described. It utilizes a specially tailored quadratic program which reduces storage requirements and improves speed of computations. Three advanced designs in the frequency domain show application.