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Basant R. Chawla

dblp:65/3951 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 1990
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 87% Integrated circuit design · 13%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › module generation
cell generation
0.011981
Automatic generation and characterization of CMOS polycells · DAC 1981
Electronic design automation
physical design
0.011981
Automatic generation and characterization of CMOS polycells · DAC 1981
Electronic design automation
circuit simulation
0.011975
Operational features of an MOS timing simulator · DAC 1975
Electronic design automation › circuit simulation › timing simulation
MOS timing simulation
0.011975
Operational features of an MOS timing simulator · DAC 1975
Integrated circuit design › ASIC design
standard cell design
0.011981
Automatic generation and characterization of CMOS polycells · DAC 1981
Integrated circuit design › digital circuit design
MOS circuits
0.011975
Operational features of an MOS timing simulator · DAC 1975
YearPublicationVenuePosition
1990 Distributed Computing Environment for Design Automation in the 90's (Panel Abstract)
Basant R. Chawla
DAC1
1981 Automatic generation and characterization of CMOS polycells
C. M. Lee, Basant R. Chawla, S. Just
DAC2
1975 Operational features of an MOS timing simulator
Paul Kozak, Herman K. Gummel, Basant R. Chawla
DAC3