This article presents hardware-efficient harmonics cancellation techniques using digital predistortion (DPD) for low-distortion sinusoidal signal generation, targeted for the dynamic characteristic testing of high-resolution 14-bit and 16-bit 1 MS/s analog-to-digital converters (ADCs) in VLSI testing environments. For 14-bit ADC testing, a single 16-bit digital-to-analog converter (DAC) with a simplified DPD circuit is demonstrated to achieve a second-order harmonic distortion (HD2) level of −92dBc. For 16-bit ADC testing, where higher resolution is required, we propose a novel dual-DAC architecture utilizing a dual-range synthesis method to enhance effective resolution and suppress harmonics up to the fifth-order (HD2–HD5). Furthermore, to minimize the hardware overhead in practical implementations, we introduce optimized field-programmable gate array (FPGA) design strategies, including time-division multiplexing (TDM) and compressed sine look-up tables (LUTs), achieving a 96.8% reduction in memory usage. The parameters are extracted via a single-step, deterministic calibration flow, ensuring high testing throughput without iterative optimization. Experimental results show HD2–HD5 levels down to −120 dBc, providing a hardware-efficient solution for high-precision built-out self-test (BOST) and future system-on-chip (SoC) integration.

This paper presents a physically unclonable function (PUF) using flash time-to-digital converter (TDC) with linearity self-calibration. The proposed PUF utilizes that the variation of delay of delay elements of TDC is unique to the device and unclonable. The proposed PUF is constructed using the flash TDC with linearity self-calibration using histogram method. With the linearity self-calibration operation, variation of delay elements is estimated. The response output of the PUF is calculated using the estimated variation and the challenge inputs. The proposed PUF is a simple digital circuit consisting of basic digital elements. It is easy to design and implement to both SoC and FPGA. It can be used as not only strong PUF but also as a TDC with fine linearity. The experimental results with Artix7 FPGA show that the intra-chip variation is 8.9 % and the inter-chip variation is 46.9 %. The probability of the correct identification is 99.8 %. Extra resources to construct the proposed PUF are 33.7 % of the resources of the TDC with linearity self-calibration.

This paper describes two harmonics cancellation techniques using digital predistortion (DPD) for low-distortion sinusoidal signal generation with direct digital synthesizer; it is targeted for the dynamic characteristic testing of 14-bit and 16-bit 1MS/s ADCs and their testing sinusoidal wave frequencies are around 100kHz. (i) The first one is an analog-intensive DPD method for the 16-bit ADC testing. The HD2 and HD3 of the original sinusoidal signal are measured with FFT method, and then their 180-degree phase-shifted signals are generated with an auxiliary DAC and added to the original signal to cancel the HD2 and HD3. Our experiments show that −120dBc of HD2 and HD3 can be achieved. (ii) The second one is a digital-intensive DPD method for the 14-bit ADC testing. The digital data of the 180-degree phase-shifted signals of the measured HD2 and HD3 are added to the original digital data of the direct digital synthesizer. The circuit is simple, and our experiments show that −92dBc of HD2 can be achieved. Their details of analysis, simulation and experimental results are shown.

This paper demonstrates that a 20-bit subrange ADC for high precision voltage measurement can be implemented with standard ATE resource and BOST circuits, without special devices. Our prototype 20-bit ADC employs subranging architecture and consists of a 16bit ADC (LTC1867), a 20-bit DAC (ADC5791), Arduino and some additional circuits. Its operation has been confirmed with simulations and experiments, and effects of non-idealities for each circuit to the overall 20-bit ADC performance have been evaluated. We consider that a 16bit audio-band digitizer in an ATE system can be used as the 16bit ADC while the 20-bit DAC as well as an error amplifier (another component for the subranging ADC) can be implemented with BOST circuits.

Testing of analog circuits plays a very important role in achieving both reliability and low cost for IoT and automotive systems. It is a technological challenge including circuit design, signal processing algorithms and measurement methods. This session consists of three talks from industry and academia in this area.

Background: In IoT system devices, currents become smaller and they have to operate for ten years with a coin cell battery. Then their accurate and fast measurement is required at the mass production shipping stage. However, the conventional method needs a large resistor (Rm, MΩ-order in Fig. 1) which makes the testing slow, and the ATE environment is noisy.Research Target: Our target is the development of a testing technique to measure the current in the order of nano or sub-nano ampere with high linearity in the noisy ATE environment and in short time as well as with only additional low cost built-out self-test (BOST) circuits.Approach: Fig. 2 shows the proposed current measurement circuits. The current under test is converted to the voltage through an op-amp and a resistor Rmof 10kΩ, and it is then converted to the AC voltage; these conversions are done with small BOST circuits. The AC voltage is amplified and converted to the digital signal through an AC amp, a sample/hold circuit and an ADC. FFT is performed and its power spectrum is calculated; the input current value is obtained. The resistor (Rm) of 10k generates spike noises which are spurious components in the power spectrum. However, usage of the sample/hold circuit reduces their effects. Thanks to the DC-AC conversion, the measurement accuracy is not degraded by the system noise in the low frequency region. The nano-ampere current and the resistor of 10kΩ produces several tens μV level voltage and our previous research in [1, 2] shows that the DC-AC conversion method can measure this level of the voltage accurately and in short time. Also, its multi-channel measurement is possible.Experiment Verification: Preliminary experiment with the prototype system in Fig. 2 was performed and its measured result is shown in Fig. 3. The measurement circuit gain in Fig. 2 was calibrated with 1.0nA input current (Iin), which corresponds to Vin of 10.0μV. Also an offset of 0.2μV due to electromotive force (EMF) was calibrated. We see in Fig. 3 that the proposed method can measure the current as low as 50pA. So far EMF limits the lowest measurable current. Fig. 4 shows 100 times of measurements for 1.0nA without averaging. Each measured current value is obtained by 1K-point FFT with 25.6 ksps, 16-bit ADC (myDAQ) usage and the measurement time of 40ms. The measured data is within 0.94nA to 1.07nA; the variation range is 0.13nAp−p.Conclusion: A method of fast and accurate current measurement as low as 50pA using IV conversion and DC-AC conversion in ATE environment has been developed.

In LSI testing, equivalent time sampling techniques are frequently used because the input signals to the device under test and the sampling clock are controllable; when the repetitive input signals are applied to the analog device under test, its output signals can be also repetitive. In this paper, we investigate an efficient waveform acquisition method with the equivalent-sampling using the metallic ratio of the sampling frequency and the input frequency, which is expected to be used for on-line, short-time and simple analog/RF/mixed-signal IC testing.

This paper demonstrates the harmonic distortion measurement of operational amplifiers by applying our proposed summing node method; we show that it can provide low-cost and high-accuracy testing at the mass production shipping stage. Experiments show that measurement accuracy below -130 dBc is possible without expensive test equipment such as an audio analyzer. We show by theory, simulations, and experiments that the summing node method makes the measurement accuracy robust to the harmonics of the signal source providing the sinusoidal input signal to the operational amplifier under test. In other words, a high precision signal generator is not required. Furthermore, we propose the false summing node method, which does not require direct probing of the summing node, in order to avoid oscillation and instability of the video-band operational amplifier under test. Simulations and experiments verify that it can achieve accurate testing without probing of the summing node and it is robust against the ratio variation of the two resistors in the false summing node testing circuit.

This paper describes that the mature ADC testing method with a simple test system using the incoherent sampling and the standard algorithm of windowing and FFT with 4Kpoint data can measure the SINAD of our target 12-bit SAR ADC accurately by proper setting of the input and sampling frequencies, which is industry-friendly. We show the input sinusoidal signal and sampling clock frequency relationship for accurate testing of the ADC dynamic characteristics with an incoherent sampling method using a flat-top window. We have clarified the measured SINAD accuracy of the input signal frequency dependency for a fixed sampling frequency, a specified resolution of the ADC under test and a given number of FFT points (data samples) in the incoherent sampling environment. Mature technology combinations with their optimal usage and without advanced methods can lead to the low-cost high-quality testing of the ADC, which can be well accepted in industry. Their analysis, simulation and experimental results are shown.

This paper proposes a summing node test method for the operational amplifier and shows the followings: (i) It can be used for parallel testing of multiple AC characteristics (such as open loop gain (AOL), PSRR and CMRR) of one operational amplifier simultaneously with the equivalent accuracy but much faster compared to the NULL method. Also it can measure them even for multiple operational amplifiers at the same time. (ii) It can measure THD, SNR and THD+N of the operational amplifier with the comparable accuracy to the audio analyzer usage case, by applying proper analog filters. In other words, it can measure them with remarkable accuracy at very low cost. These have been verified with simulations and experiments. The proposed summing node test method uses an inverting operational amplifier under test and its negative input is amplified by an auxiliary non-inverting operational amplifier. The input and power supply voltages for the operational amplifier under test are modulated by AC signals with different frequencies. The auxiliary amplifier output is digitized after analog filtering and FFT is performed to the digitized data. This proposed method can reduce operational amplifier test time with good accuracy but without expensive instruments at mass production shipping, to meet the requirements for IoT and automotive as well as audio applications.

This paper describes an accurate and fast testing technique for a precision voltage reference. Our proposed DC-AC conversion and FFT spectrum analysis method is applied and its experiment results show that measurement accuracy within ±100μV and measurement variation (repeatability) within ±10μV are feasible.

The IP session highlights three innovative test practices in Asia, which include a testing solution for the millimeterwave (76- to 81- GHz) without expensive instruments, an on-chip delay measurement method for in-field test and a power control method of at-speed scan test for IR violation reduction. These would be useful for automotive and IoT application device testing.

This paper describes an accurate and fast testing technique for small DC offset voltage of a high precision operational amplifier. Chopper techniques for DC-AC conversion and FFT spectrum analysis are combined and then accurate DC voltage measurement on the order of μV can be achieved. We have also investigated thermo-electromotive force effects and their countermeasures. Their simulations and experiments with prototype measurement systems have been carried out, and the measurement linearity up to as low as 0.2 μV of the DC measurement voltage was confirmed. We have also investigated its extension to multi-channel realization for short testing time.

The IP session highlights three innovative test practices in Japan, which include DC parametric test time reduction using digital controlled DC resource and deep reconsideration for ADC distortion testing as well as test time reduction of low sampling rate and high-resolution ADC linearity. These would be useful for automotive and IoT application device testing.

The IP session highlights three innovative practices in Asia, which include low cost testing of analog front-end circuits, evaluation of complex analog filter and power reduction of power-on self-test for automotive MCU.

Start of the above-titled section of the conference proceedings record.

Start of the above-titled section of the conference proceedings record.

Multi/many-core processors allow to handle path delay faults although the number of paths exponentially grows with the circuit size. This paper proposes an efficient path delay fault simulation that identifies all the robust and non-robust testable path delay faults for each test pattern. The simulation result is expressed by a scalable data structure only proportional to the numbers of gates and test patterns. The proposed simulation uses two types of parallelism, bit- and thread-parallelism, while considering efficient usage of multiple computing units and SIMD units which is resulting in a very fast simulation. Experimental results demonstrate the efficiency of the proposed method identifying all the robust and non-robust testable paths for a large number of test patterns. In addition, the simulation surpasses a commercial logic simulator which just processes a part of the proposed method.

This paper presents a scan-based BIST architecture for FPGAs used as application-specific embedded devices for low-volume products. The proposed architecture efficiently utilizes memory blocks, instead of logic elements, to build up BIST components such as LFSR, MISR and scan chains for test points. It also provides enhanced scan functionality for test points and performs a hybrid test application of LOC and enhanced scan to improve delay test quality. Experimental results show that the proposed BIST architecture achieves high delay test quality with efficient resource utilization.

In this paper, we propose a process-variability-aware adaptive test flow that realizes efficient and comprehensive detection of parametric faults. A parametric fault is essentially a malfunction in a large-scale integration chip, which is caused by the variability in fabrication processes. In our adaptive test framework, test pattern sets are altered on individual chips in order to apply the optimal set of test patterns for each chip, and thus the test coverage is improved and the test time is reduced. The test pattern is chosen on the basis of parameter estimations measured using an on-chip sensor with respect to statistical timing information. We also propose a novel metric to quantize the test coverage suitable for evaluating the test quality of parametric faults. Our experimental results using an industrial design show that the proposed flow significantly improves the parametric fault coverage and test efficiency compared to conventional test flows.

Start of the "Special session 4B: Elevator talks" section of the conference record.

Although many electronic safety-related systems require very high reliability, it is becoming harder and harder to achieve it because of delay-related failures, which are caused by decreased noise margin. This paper describes a technology named DART and its implementation. The DART repeatedly measures the maximum delay of a circuit and the amount of degradation in field, in consequence, confirms the marginality of the circuit. The system employing the DART will be informed the significant reduction of delay margin in advance of a failure and be able to repair it at an appropriate time. The DART also equips a technique to improve the test coverage using the rotating test and a technique to consider the test environment such as temperature or voltage using novel ring-oscillator-based monitors. The authors applied the proposed technology to an industrial design and confirmed its effectiveness and availability with reasonable resources.

In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel per-cell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IR-drop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency.

A novel technique that estimates on-chip process parameters, such as threshold voltages or channel length, is proposed. The proposed method is particularly useful as process condition estimator for reliability and yield enhancement techniques such as adaptive delay test or post-fabric performance compensation. Test paths consisting of a flip-flop and designated delay circuit, which is sensitive to individual process parameters, are inserted to obtain simultaneous delay inequalities. Then, the inequalities are solved for process parameters. The test path insertion is only on short paths to reduce delay and area overhead. Through numerical experiments, the proposed estimation flow using 150 paths achieve 10mV accuracy in estimating threshold voltages.

Adaptive test is one of the most efficient techniques that practically ensure high yield and reliability of designed chips. In this paper, a novel path-clustering method suitable for the adaptive test, in which test paths are altered according to the monitored process-parameters, is proposed. Considering the probability function of the die-to-die systematic process variation, the proposed method clusters path sets so that the total number of test-paths are minimized. For quantitative evaluation of different clusterings, figure of merit for clustering, which represents the expected number of test-paths at a particular test coverage, is also proposed. The proposed clustering is experimentally evaluated by applying to an industrial circuit. With our clustering, the average test paths in the adaptive test have been reduced to less than 50% compared with the ones of the conventional test.

The continuing miniaturization of LSI dimension is causing the increase of process-related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.

Reducing IR-drop in the test cycle during at-speed scan testing has become mandatory for avoiding test-induced yield loss. An efficient approach for this purpose is post-ATPG test modification based on X-identification and X-filling since it causes no circuit/clock design change and no test vector count inflation. However, applying this approach to test compression has been considered challenging due to the limited availability of X-bits. This paper solves this serious problem by proposing a novel and practical CA (Compression-Aware) test modification scheme for reducing IR-drop in the widely-used broadcast-scan based test compression environment. This unique scheme features (1) CA circuit remodeling for minimizing the effort of applying test modification to broadcast-scan-based test compression, (2) CA X-identification for increasing X-bits for risky test vectors, and (3) CA X-filling for effectively using limited X-bits in reducing IR-drop. As a result, the CA test modification scheme can achieve significant IR-drop reduction even when a test cube only has a small number of X-bits. This advantage is clearly demonstrated by experimental results on three compression configurations created from an industrial circuit.

We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering both the location and the resistance distribution, and the simplified one where str and stf faults considering the signal transition of the input ports are assumed. The coverage calculation for the primitive gates and small benchmark circuit reveals that the proposed models have more accuracy on the detection of weak open defects.

Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.

Test data modification based on test relaxation and X-filling is the preferable approach for reducing excessive IR-drop in at-speed scan testing to avoid test-induced yield loss. However, none of the existing test relaxation methods can control the distribution of identified don’t care bits (X-bits), thus adversely affecting the effectiveness of IR-drop reduction. In this paper, we propose a novel test relaxation method, called Distribution-Controlling X-Identification (DC-XID), which controls the distribution of X-bits identified from a set of fully-specified test vectors for the purpose of effectively reducing IR-drop. Experimental results on large industrial circuits demonstrate the effectiveness and practicality of the proposed method in reducing IR-drop, without any impact on fault coverage, test data volume, or test circuit size.

As a method to evaluate delay test quality of test patterns, SDQM (Statistical Delay Quality Model) has been proposed for transition faults. In order to derive better test quality by SDQM, the following two things are important: for each transition fault, (1) to find out the accurate length of the longest sensitizable paths along which the fault is activated and propagated, and (2) to generate a test pattern that detects the fault through as long paths as possible. In this paper, we propose a method to calculate the length of the potentially sensitizable longest path for detection of a transition fault. In addition, we develop a procedure to extract path information that helps high quality transition ATPG. Experimental results show that the proposed method not only derives more accurate SDQL (Statistical Delay Quality Level) but also enhances the test quality of generated test patterns.

In this session, various case studies of leading edge SoCs testing are presented with advanced ideas for effective and efficient testing.

Logic BIST is well known as an effective method for low cost testing. However, it is difficult to realize at-speed testing, as it requires a deliberate timing design in regard to logic design and layout of the chip. This paper presents a timing design methodology for at-speed BIST, using a multiple-clock domain scheme. Some experimental test results of large industrial designs using our custom fool "Singen", will also be shown.

This paper presents an at-speed built-in test method for logic circuits with multiple clocks. It is clear that BIST (built-in self-test) plays a key role in test strategy for SoCs. It is also obvious that at-speed BIST is necessary for high quality test. Though several approaches enable at-speed BIST, there still exist several issues, such as multiple clocks, multi-cycle transfers and false paths. The proposed method realizes at-speed test for arbitrary combination of release and capture clocks at reasonable test time by utilizing the LFSR reseeding technique. Experimental results for benchmark circuits and an industrial circuit are given to illustrate the effectiveness of our approach.

This paper presents an approach for high-quality built-in test using a neighborhood pattern generator (NPG). The proposed NPG is practically acceptable because (a) its structure is independent of circuit under test, (b) it requires low area overhead and no performance degradation, and (c) it can encode deterministic test cubes, not only for stuck-at faults but also transition faults, with high probability. Experimental results for large industrial circuits illustrate the efficiency of the proposed approach.

Presents a practical coverage metric in delay testing, which is called a multiple-threshold gate-delay fault model, to obtain high quality tests for large circuits. Fault efficiencies for given multiple thresholds of the delay fault size are computed, and their entirety describes the quality of tests. The approach guarantees that each gate-delay fault is not only robustly tested on almost the longest path, but also tested under the condition as a transition fault, by using two-pattern tests with a pattern-independent timing. We present procedures of path selection, fault simulation and test generation, where the path-status graph technique is used for an efficient computation. Experimental results for industrial circuits demonstrate that the proposed method can achieve high fault efficiencies for gate-delay faults having various fault sizes in a practical processing time.

This paper presents a practical test point insertion method for scan-based BIST. To apply test point insertion in actual LSIs, especially high performance LSIs, it is important to reduce the delay penalty and the area overhead of the inserted test points. Here efficient test point selection algorithms, which are suitable for utilizing overhead reduction approaches such as restricted cell replacement, test point flip-flops sharing, are proposed to meet the above requirements. The effectiveness of the algorithms is demonstrated by some experiments.

This paper presents a design for delay testability approach to improve delay fault coverage for high speed logic LSIs. In order to simplify the model for delay test generation from two stage combinational circuit model to ordinary combinational circuit model, we add an extra latch, called sub-latch for each scannable flip-flop. A procedure for delay test generation is also developed to establish high fault coverage. The results for a practical application to logic LSIs used in mainframe computers is given to illustrate the effectiveness of our approach.

This paper presents an accelerated test points selection method for circuits designed by a full-scan based BIST scheme. In order to speed up the test points selection method based on cost minimization, and reflecting random pattern testability, we introduce three techniques, the simultaneous selection of plural test points, the simplified selection of test points by the cost reduction factor, and the reduction of the number of test point candidates. We implement a program based on the proposed method and evaluate its efficiency experimentally using large scale circuits (26 k-420 k gates).

This paper presents a practical approach to functional test pattern generation for gate level faults in functional modules of VLSI processors. Test patterns are generated by constrained test generation and translated to functional test patterns, each of which is a sequence of instructions. In this paper, the outline of instruction-based test generation system, ALPS, is given first, and then constrained test generation is described in detail. Finally, the result of practical application to a VLSI processor is given to illustrate the effectiveness of our approach.

This paper presents a parallel, automatic test generation system, DESCARTES, for synchronous sequential circuits. This system parallelizes the test generation algorithm based on real-valued logic simulation. By addition of a redundant fault identification program and an algorithmic test generation program, test generation is speeded up and test quality is improved. Experimental results for ISCAS '89 benchmark sequential circuits illustrate the efficiency of this approach.

This work presents an approach to the test generation for synchronous sequential circuits. This approach utilizes an extended logic simulation, called real-valued logic simulation, and solves the sequential test generation problem as a kind of optimization problem. The approach has the possibility of high speed test generation, because high speed processing techniques, such as, vector processing, parallel processing, and so on, can be efficiently applied to the most time-consuming part of this approach. Experimental results for ISCAS'89 benchmark sequential circuits also illustrate the eficiency of this approach.

An enhanced delay test generation procedure for high-speed logic LSIs is presented. The procedure is applicable to general scan-designed sequential circuits including both level-type flip-flops and edge-type flip-flops. Some techniques are introduced to solve the problem of 'same-clock signal transfer' between these flip-flops and to enhance the performance of the delay test generation procedure. The effectiveness of the procedure is demonstrated by the experimental results obtained.>