The deployment of large language models (LLMs) is critically dependent on the key-value (KV) cache. However, the “write-less, read-many” access pattern of the SRAM tier of KV cache in LLMs poses a reliability challenge. Combined with CMOS scaling, it markedly accelerates aging mechanisms like bias temperature instability (BTI). BTI increases the threshold voltage and slows the devices, posing a severe threat to the reliability of the high-speed KV Cache SRAMs. To address this challenge, this paper proposes an architecture that couples in-situ, path-faithful sensing while exposing interfaces and guidance for system-level reliability management. In this paper,First, we propose an aging-enhanced SRAM cell and sensing amplifier (SA) and their configurable circuit topology to support an aging sensing interface.Second, we present a reconfigurable TDC-based in-situ aging detection circuit. It either detects the aging of cells through the aging sensing interface or replaces the aged cells to maintain their original timing performance.Third, we present a lifetime management strategy that uses the aging detection circuit to monitor the aging status of memory, control its operation modes, and alert its end-of-life alarm. A 28-nm 64-Kbit memory circuit has been constructed to validate the optimizations above. Experiment results show that our proposed aging-aware memory achieves a lifetime of 13.1 years, and after 10 years of operation, the presented aging-aware memory can achieve a maximum operating frequency of 1.47 GHz. Compared with state-of-the-art designs, our proposed design achieves a system lifetime improvement of$\gt 3.9\times $, a maximum SA FoM of 29.5, which is about$2\times $that of SOTA SA designs.

Quantum annealing algorithms have shown commercial potential in solving some instances of combinatorial optimization problems. However, existing mapping for general optimization problems into a compatible format for quantum annealing yields dense topology and complicated weighting, which limits the size of solvable problems on practical quantum annealing machines. To address this issue, we propose a novel mapping framework with three new techniques. First, to address the issue from general constraints, we introduce a recursive methodology to map constraints into interconnected Boolean gates and small algebraic cliques, which yields sparse topology and hardware-friendly biases/interactions. Second, to better address frequently-used constraints, we introduce a specialized penalty set based on this methodology with detailed optimizations. Third, to address the issue from the objective, we reformulate the complicated objective into a single multi-bit variable and apply binary search to its range, which turns each search step into a constraint-only problem. Compared with the state-of-the-art, experimental results and analysis over an exhaustive scan for operand bit-widths from 1 to 64 show that: (1) the growth order of the number of physical qubits with regard to operand bit-widths is reduced fromO(w2) toO(w), while the number is reduced by a factor of 10-1 in the best case; (2) the dynamic range of biases/interactions is reduced fromO(22w) to−2in the best case. For the same optimization problem, our framework reduces the requirement of the number of physical qubits and machine precision, and shortens the time from problem to machine.

Emerging applications are calling for significantly larger FPGAs with multi-dies. However, the interconnection architecture of existing FPGAs lacks scalability. The execution time and failure probability of their RTL-to-Silicon process increase dramatically with the growth of design and the number of dies. To address this issue, we propose both an NoC-based scalable multi-die FPGA architecture and a corresponding floorplanning framework, namely Hierarchical and Recursive Floorplanning Framework(HRFF). First, from the architecture side, we introduce an interconnection architecture with a class of scalable hierarchical topology. Second, for the algorithm side, we formulate the generic floorplanning problem for NoC-based architectures as a multi-objective Mixed Integer Linear Programming (MILP) problem, balancing the design timing and interconnection workload. Third, we develop a novel recursive approximate method to efficiently solve the multi-objective MILP formulation over the proposed architecture, with a configurable trade-off between solution quality and solver run time. Experimental results show that the scalability of our proposed technique is at least$1.5 \times $on all and$3 \times $on certain benchmarks as that of the state-of-the-art solutions with no loss of design throughput.

Non-Line-of-Sight (NLOS) imaging reconstructs occluded scenes based on indirect diffuse reflections. The computational complexity and memory consumption of existing NLOS reconstruction algorithms make them challenging to be implemented in real-time. This paper presents a fast and memory-efficient phasor field-diffraction-based NLOS reconstruction algorithm. In the proposed algorithm, the radial property of the Rayleigh Sommerfeld diffraction (RSD) kernels along with the linear property of Fourier transform are utilized to reconstruct the Fourier domain representations of RSD kernels using a set of kernel bases. Moreover, memory consumption is further reduced by sampling the kernel bases in a radius direction and constructing them during the run-time. According to the analysis, the memory efficiency can be improved by as much as 220×. Experimental results show that compared with the original RSD algorithm, the reconstruction time of the proposed algorithm is significantly reduced with little impact on the final imaging quality.