Neural Assembly Computing (NAC) is a biologically inspired framework that uses spiking neural networks (SNNs) to simulate the computational processes of neural cell assemblies. Building on earlier research, we propose an extended NAC-based state machine capable of recognizing significant patterns and predicting the next symbol in a sequence. The model employs four states that reflect the activity of neural assemblies to process sequences consisting of distinct symbols. The proposed system achieves real-time sequence prediction and demonstrates robustness under noisy conditions by learning probabilistic relationships between symbols during training. The simulation results highlight the ability of the network to identify incomplete sequences and anticipate subsequent input, showcasing the potential of NAC as an efficient and biologically realistic approach for intelligent systems, robotics, and adaptive decision-making applications.

This article presents a comparative study of sampling methods within the FedHome framework, designed for personalized in-home health monitoring. FedHome leverages federated learning (FL) and generative convolutional autoencoders (GCAE) to train models on decentralized edge devices while prioritizing data privacy. A notable challenge in this domain is the class imbalance in health data, where critical events such as falls are underrepresented, adversely affecting model performance. To address this, the research evaluates six oversampling techniques using Stratified K-fold cross-validation: SMOTE, Borderline-SMOTE, Random OverSampler, SMOTE-Tomek, SVM-SMOTE, and SMOTE-ENN. These methods are tested on FedHome's public implementation over 200 training rounds with and without stratified K-fold cross-validation. The findings indicate that SMOTE-ENN achieves the most consistent test accuracy, with a standard deviation range of 0.0167–0.0176, demonstrating stable performance compared to other samplers. In contrast, SMOTE and SVM-SMOTE exhibit higher variability in performance, as reflected by their wider standard deviation ranges of 0.0157–0.0180 and 0.0155–0.0180, respectively. Similarly, the Random OverSampler method shows a significant deviation range of 0.0155–0.0176. SMOTE-Tomek, with a deviation range of 0.0160–0.0175, also shows greater stability but not as much as SMOTE-ENN. This finding highlights the potential of SMOTE-ENN to enhance the reliability and accuracy of personalized health monitoring systems within the FedHome framework.

Spiking Neural Networks (SNNs) hold significant potential for achieving low-power computational capabilities in artificial intelligence (AI) applications. In this brief a low-power frequency-driven mixed-mode complementary metal-oxide-semiconductor (CMOS) circuit based on the leaky integrate-and-fire (LIF) neuron model is proposed. The dynamic behavior of the proposed structure is modeled by the frequency adjustment and the proposed circuit can model dynamic behavior without the need for an external voltage source. Furthermore, the mixed-mode circuit is not sensitive to process, voltage, and temperature (PVT) variation effects. Tailored for large-scale SNN deployment and neuromorphic algorithm realization, the design draws inspiration from a monostable block to generate spikes in the neural model’s output. The proposed circuit consists of two main parts: the neuron circuit generating output spikes and a transmission circuit connecting neurons. Simulation results vividly showcase various spiking behaviors akin to those observed in biological neurons. Noteworthy is the careful crafting of the neuron model using a 45 nm CMOS process, resulting in a mere 2.4 nW power consumption with a 1.4 V headroom voltage for multi-spiking events.

Neuromorphic computers have been presented as alternatives to traditional von Neumann systems. Neuromorphic systems mimic neural structures of the human brain to make the energy-efficient and high-performance computations. This paper proposes high-speed with no DSP resources FPGA implementation of the SAM neuron model and its fully connected networks with random synaptic weights. The synthesis reports of the implemented SAM neuron with 50, 100, 500, 1000, 2000, 4000, 6000, and 8000 random inputs have been presented. Also, the results of the synthesized fully connected populations comprising 50, 100, 500, 1000, and 1500 SAM neurons have been reported. Accordingly, the FPGA synthesis results of the proposed spiking neuron and networks are noteworthy compared to the state of the arts in terms of performance and DSP resources.

The neuron can be called the main cell of a nervous system that can transmit messages from one neuron to another neuron or another cell through electrical signals. In neuromorphic engineering, the hardware realization and simulation of these neurons are crucial. To accomplish a proper digital implementation (i.e. reducing hardware resources and increasing speed and accuracy) of three important neuron models including Hodgkin-Huxley, Morris-Lecar, and Izhikevich, this study proposes a set of multiplier-less mathematical equations based on converting nonlinear functions to$2^{x}$functions. Then optimizes the proposed equations based on reducing the number of different$2^{x}$terms. The suggested model can accurately recreate the behavioral characteristics of the original neuron models. The suggested model was synthesized and implemented on the Zynq XC7Z010 (3CLG400) reconfigurable board (FPGA) to validate the mathematical simulation findings. The results of hardware synthesizing and implementations of the proposed model show that different biological behavior can be replicated with greater efficiency and at substantially reduced implementation costs. This method (implemented on the zynq board) can raise the frequency of the proposed models at least by up to 3.5 times that of the original model and reduce power consumption between 20% and 60% for different proposed models. Also, due to the reduction of hardware resources in the proposed model, it is possible to implement a much larger number of neurons (between 4 and 12 times) relative to the original model on a single zynq board.

This paper proposes design of a memristive crossbar array using the VTM-NAND logic gate. The novelty of this work is its diagonal computations using the proposed cellular arrangement to implement various logical functions. Some circuit examples are given and simulated using SPICE model of memristor with nonlinear dopant drift and 180 nm complementary metal oxide semiconductors (CMOS) technology.

We propose a novel Physical Unclonable Function (PUF) derived from the neuron used in the octopus retina. The signature obtained from a single neuron has been utilized to extract digital fingerprints uniquely for every single neuron. The proposed circuit topology has been investigated from a theoretical standpoint targeting new hardware-based security mechanisms obtained from intrinsic variations in the fabrication process of Spiking Neural Networks (SNNs). The uniformity, robustness and reliability of the proposed PUF have been verified by mean of the proposed analytical models aiming at developing new methodological approaches for the design of secure PUFs resilient to the adversarial Machine Learning attacks.

In recent years, hardware modeling for various parts of the body’s sensitive organs, including the brain and nervous system, heart and eyes, has been considered for the treatment of diseases and rehabilitation, as well as for moving towards the construction of artificial prostheses. The retina is a thin layer that is the innermost layer of the human eye. In this paper, low-cost hardware implementation for retinal cone cells is performed. Existing mathematical models for implementing the behavior of these cells include a series of nonlinear functions that, if implemented directly, would require a large amount of hardware and, in addition, would not have the desired speed. The proposed model uses multi-linear functions to approximate the nonlinear terms and eliminate the multiplication expressions. The simulation results show that the proposed model tracks the behavior of the original model with high precision. There is also a good match between the main model and the proposed model in terms of dynamic behaviors. The results of hardware implementation using the virtex5 XC5VLX20T (2FF323) reconfigurable board (FPGA) show that the proposed model is fully valid and has a lower hardware volume as well as a 4 times higher frequency, and 22% less power consumption than the original model.

Neurons are the basic blocks in the Central Nervous System (CNS). Simulation and hardware realization of these blocks are vital in neuromorphic engineering. This paper presents a set of multiplierless mathematical equations based on 2Xterms to achieve a low-cost, high-speed, and high-accuracy digital implementation of Hodgkin-Huxley (HH) neuron model. The HH model is the most complicated and high-accuracy among the mathematical neuron models. The proposed model can reproduce spiking behaviors of the original HH model with high precision. To validate the mathematical simulation results, the proposed model has been synthesized and implemented on Field-Programmable Gate Array (FPGA) development board. Hardware synthesis and physical implementations reveal that the biological behavior of different spiking patterns can be reproduced with higher performance and significantly lower implementation costs compared with the original HH model. Also, in this approach the maximum frequency of 200 MHz is achievable which is valuable in comparison with other similar works.

Spiking neurons, the models that mimic the biological cells in the brain, are described using ordinary differential equations. A common method to numerically solve these equations is Euler's method. An important factor that has a significant impact on the performance and cost of the hardware implementation or software simulation of spiking neural networks and yet its importance has been neglected in the published literature, is the time step in Euler's method. In this paper, first the Izhikevich neuron's accuracy as a function of the time step was measured. It was uncovered that the threshold time step that Izhikevich neuron becomes unstable is an exponential function of the input current. Software simulation performance, including total computational time and memory usage were compared for different time steps. Afterwards, the model was synthesized and implemented on the Filed Programmable Gate Array (FPGA). Hardware performance metrics such as speed, area and power consumption were measured for each time step. Results indicated that time step has a negative linear effect on the performance. It was concluded that by determining maximum input current to the neuron, larger time steps comparable to those used in the previous works could be employed.

Summary form only given. This paper proposes a neuromorphic platform for on-FPGA online Spike Timing Dependant Plasticity (STDP) learning, based on the COordinate Rotation DIgital Computer (CORDIC) algorithms. The implemented platform comprises two main components. First, the Izhikevich neuron model is modified for implementation using the CORDIC algorithm, simulated to ensure the model accuracy, described as hardware, and implemented on FPGA. Second, the STDP learning algorithm is adapted and optimized using the CORDIC method, synthesized for hardware, and implemented to perform on-FPGA online learning on a network of CORDIC Izhikevich neurons to demonstrate competitive Hebbian learning. The implementation results are compared with the original model and state-of-the-art to verify accuracy, effectiveness, and higher speed of the system. These comparisons confirm that the proposed neuromorphic system offers better performance and higher accuracy while being straightforward to implement and suitable to scale.

Memristor crossbar architectures are considered as one of the most promising platforms for future memory, logic, and in-memory computing applications. This paper presents a 2M1M crossbar architecture, capable of memory and logic applications, based on a transistor-less memory cell, which behaves as a switching circuit. The proposed memory cell consists of two access and one target memristors that utilize a gating structure by access devices to reduce sneak path effect. This paper has considerably lower wiring density and lower number of memristors per bit compared with its peers. Therefore, it can be a suitable structure for high-density memory and logic applications. In addition to its in-memory computing capabilities, 2M1M structure as a memory offers higher density and less energy consumption in comparison with conventional CMOS-based static random access memory. In comparison with previous works, simulation results show significant improvements in basic implementation costs of the memory cell in terms of write time (1.11 ns), read time (200 ps), density (80 Gb/cm2), energy consumption (23.2 × 10-3fJ/bit), and wiring complexity. Also, it has a sneak path current of 90-nA per memory cell operation which is considerably lower compared with its peers.

These days, there is an increasing interest in implementation of spiking neural systems that can be used to perform complex computations or solve pattern recognition tasks like mammalian neocortex. In this paper, Morris-Lecar neuron neuron is utilized to implement bio-inspired memristive spiking neural network for unsupervised learning applications. The spike timing dependent plasticity learning mechanism has been applied as the learning scheme in the system. The memristive implementation of the Morris-Lecar neuron has been analyzed. Also the memristors are utilized as the synapses for the proposed system to reproduce long term potentiation and long term depression. The proposed platform is tested for pattern classification applications and the results are successfully confirmed its functionality.

Security is the main challenge in the design and implementation of today's ubiquitous interconnected objects on the Internet network infrastructure. Many security solutions have been already proposed to address security concerns for IoT enabled devices. In this paper, an integrated approach for authentication and access control is presented for communication with wireless sensor nodes in IoT networks. The proposed method provides strong protection against known attacks such as energy exhausting, and Man-In-The-Middle.

This paper presents a Genetic Algorithm (GA) based evolution framework in which Spiking Neural Network (SNN) of single or a colony of artificial creatures are evolved for higher chance of survival in a virtual environment. The artificial creatures are composed of randomly connected Izhikevich spiking reservoir neural networks. Inspired by biological neurons, the neuronal connections are considered with different axonal conduction delays. Simulation results prove that the evolutionary algorithm has the capability to find or synthesis artificial creatures which can survive in the environment successfully and also simulations verify that colony approach has a better performance in comparison with a single complex creature.

In this paper we propose a hardware implementation of a new deep brain stimulator that is able to desynchronize an abnormally synchronized neural population model. The proposed stimulator is based on a delay feedback technique and is applied on a population of neurons described with Izhikevich model. The whole structure of the stimulator and the neural population model are first simulated in software and then implemented on hardware FPGA platform. The results of software/hardware simulation/implementation show that the proposed stimulator has a good performance and is able to desynchronize a hyper-synchronized neuronal population model.

It is expensive to simulate large-scale neural networks on hardware while ensuring a high resemblance to the original neurons' behavior. This paper introduces a novel technique to facilitate digital implementation and computer simulation of neuron models that contain an exponential term. This technique is applied to a biologically realistic neuron model called Adaptive Exponential integrated and fire (AdEx). Hardware synthesis and physical implementations show that the resulting model can reproduce precise neural behavior with high performance and considerably lower implementation costs compared with the original AdEx model.

Memristor-based arithmetic circuits promise new alternatives for their conventional CMOS-based peers due to memristor' s scalability and non-volatility features. In-memory memristor-based calculations become extensively attractive as it can be a solution to tackle memory bottleneck problems and also an ingredient for future beyond Von-Neumann computer architectures. In this paper material implication-based designs for 4:2 compressor cells using memristor devices are presented. A physical model is applied to determine real switching speed of memristive device. The proposed parallel design promises good speed performance with considerably less area than conventional CMOS designs. Finally a comparison has been made between the proposed memristor-based and CMOS-based designs in terms of number of applied devices per cell and delay.

In this paper an analog cellular neural network is proposed with application in physical unclonable function design. Dynamical behavior of the circuit and its high sensitivity to the process variation can be exploited in a challenge-response security system. The proposed circuit can be used as unclonable core module in the secure systems for applications such as device identification/authentication and secret key generation. The proposed circuit is designed and simulated in 45-nm bulk CMOS technology. Monte Carlo simulation for this circuit, results in unpolarized Gaussian-shaped distribution for Hamming Distance between 4005 100-bit PUF instances.

In this paper, design of a passive resistive-type neuron is proposed to generate the hyperbolic tangent function as the activation function. The proposed resistive-type neuron has the advantage of not needing any biasing voltage and therefore its power consumption is low. The neuron circuit is designed and simulated in 180 nm CMOS technology. The proposed neuron shows a good approximation with maximum error and average error from the ideal hyperbolic tangent function by 19.7% and 6.88% respectively. The power consumption of the proposed neuron is 62.5 μW while the standby power is zero. Also the proposed neuron is applied in a large neural network and the results shows good functionality. The pattern recognition neural network implemented using the proposed neuron is consumed 295 μW power that is approximately 59.86% less than the same network proposed with the previous analog hyperbolic tangent designed neuron.

This paper presents a modified astrocyte model that allows a convenient digital implementation. This model is aimed at reproducing relevant biological astrocyte behaviors, which provide appropriate feedback control in regulating neuronal activities in the central nervous system. Accordingly, we investigate the feasibility of a digital implementation for a single astrocyte and a biological neuronal network model constructed by connecting two limit-cycle Hopf oscillators to an implementation of the proposed astrocyte model using oscillator-astrocyte interactions with weak coupling. Hardware synthesis, physical implementation on field-programmable gate array, and theoretical analysis confirm that the proposed astrocyte model, with considerably low hardware overhead, can mimic biological astrocyte model behaviors, resulting in desynchronization of the two coupled limit-cycle oscillators.

This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical algorithms always results in an optimization problem of trading computational error with implementation costs. In this study, a symbolic noise analysis method is introduced for high-level synthesis, which is based on symbolic modeling of the error bounds where the error symbols are considered to be specified with a probability distribution function over a known range. The ability to combine word-length optimization with high-level synthesis parameters and costs to minimize the overall design cost is demonstrated using case studies.

A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of functional units has a great impact on design costs. A combination of both methods is used in this paper in the form of a partitioned shared bus structure, in which every partition has a different width and all the functional units connected to a bus partition have the same input/output word-lengths. Having controlled the group binding and word-length of the FUs as well as the other synthesis parameters, a high-level synthesis tool is introduced to implement DSP algorithms in digital hardware. The tool uses a multi-objective optimization genetic algorithm to minimize the circuit area, delay, power consumption and digital noise by selecting an optimal grouping and word-length for each FU in a shared bus system. Results demonstrate that savings can be made in the overall system costs by applying this method.