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G. K. Maa

dblp:65/4400 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 61% Processor architecture and microarchitecture · 30% Performance modeling and evaluation · 9%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
dataflow architecture
0.011988
Assessing the benefits of fine-grain parallelism in dataflow programs · SC 1988
Parallel and multicore computing › parallelization strategies
fine-grained parallelism
0.011988
Assessing the benefits of fine-grain parallelism in dataflow programs · SC 1988
Parallel and multicore computing › parallel computing › parallel program analysis
parallelism profiling
0.011988
Assessing the benefits of fine-grain parallelism in dataflow programs · SC 1988

Methods — techniques the papers use, named apart from their topics

parallelism profiling · 0.0dataflow graph interpretation · 0.0
YearPublicationVenuePosition
1988 Assessing the benefits of fine-grain parallelism in dataflow programs
abstract
A method for assessing the benefits of fine-grain parallelism in actual programs is presented. The method is based on parallelism profiles and speedup curves derived by executing dataflow graphs on an interpreter under progressively more realistic assumptions about processor resources and communication costs. It is shown that programs, even using traditional algorithms, exhibit ample parallelism when parallelism is exposed at all levels. Since only dataflow graphs compiled from the high-level language Id are considered, the bias introduced by the language and the compiler is examined. A method of estimating speedup through analysis of the ideal parallelism profile is developed, avoiding repeated execution of programs. It is shown that the fine-grain parallelism can be used to mask large, unpredictable memory latency and synchronization waits in architectures using dataflow instruction execution mechanisms. The effects of grouping portions of dataflow programs, such as function invocations or loop iterations, and requiring that the operators in a group execute on a single processor, are explored.>
David E. Culler, G. K. Maa
SC2