Detection of open defects in static random access memory (SRAM) cells, including those causing data retention faults (DRFs), is known to be difficult and time consuming. This paper proposes a novel design-for-test (DFT) technique that allows SRAMs to be tested at full speed for these defects. As a result, it achieves not only significant test time reduction but also full coverage of open defects, including those undetectable to previous solutions. The proposed technique is referred to as predischarge write test mode (PDWTM). Implementation of the proposed technique requires little design effort and imposes negligible hardware and performance penalties. Furthermore, the proposed technique can be easily merged with any March algorithm, thus resulting in full DRF and other SRAM cell open defect coverage. The proposed technique has been validated by SPICE simulation using both low-power and high-speed SRAM cells.

This paper addresses the test power model problem for embedded SRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a single-rectangle power model to describe their test power consumption. This leads to significant waste of test time since e-SRAM test usually includes a long period of zero power consumption for the detection of Data Retention Faults. This paper takes advantage of this zero power period and proposes a retention-aware test power model for e-SRAMs. The proposed model is evaluated and its impact on test time reduction is reported for various scenarious in terms of retention test duration, memory capacities, test algorithm complexities, etc. A formula is derived to predict the maximum test time reduction when the zero power period is fully utilized in a SoC environment.

Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typically time-consuming due to the required pause time that needs to be introduced in the test session. This paper proposes a novel technique, referred to as pre-discharge write test mode (PDWTM), that effectively integrates the testing of DRF within "regular" March algorithms such that the rate (speed) of the latter remains unaltered. That is, the PDWTM enables DRF testing without incurring the additional cycles or pauses in the March test execution thereby enabling additional coverage at no expense in terms of overall test time. We show that DRFs can be easily detected by pre-discharging bit lines before a write operation. Here, the PDWTM is evaluated using both high-speed and low power memory cells, representing two extreme cases based on the typical memory design methodologies.

Increasingly dense SRAMs of various bit capacities, embedded within current and future systems-on-a-chip (SoC) designs, command not only additional complexity due to required redundancy schemes, but also present serious challenges in regards to testing. In particular, the time needed for testing data retention faults (DRFs) and non-DRFs is growing rapidly. In this paper, we consider the overall production gain (OPG) and delay time associated with the testing of DRFs as the two selection factors for classifying embedded SRAMs, where OPG quantifies the trade-offs between yield and redundancy area overhead. These embedded SRAMs are categorized into four categories for testing non-DRFs and DRFs. Since both factors above are related to memory capacity, the four categories are named as very small, small, large, and very large types. According to this simple classification, we generate a set of four March test algorithms from an existing March SRD algorithm for each category respectively. As a comparison with March SRD, our investigations reveal that test time can generally be at least halved down to 22 nm technology for all capacity e-SRAMs with different IO numbers without losing defect coverage. The evaluation results also show that this reduction ratio is always no less than 50% for those with larger and larger and larger capacity predicted for future e-SRAMs in ITRS documents no matter what complex the comparison algorithms besides March SRD are.