This paper presents an energy-efficient continuous-time delta-sigma modulator (CTDSM) with current-reused amplifiers. The third-order single-bit modulator with finite impulse response (FIR) DAC is adopted for its superior linearity performance. In the first integrator, a two-stage hybrid compensated topology is used to achieve high gain and low noise. Meanwhile an inverter-based two-stage amplifier with a class-AB output stage is proposed for second and third integrators, achieving 2× efficiency compared to the conventional one. The proposed modulator was fabricated in 55nm CMOS process with an active area of 0.24mm2. Thanks to the current-reused amplifiers, this CTDSM consumes only 133μW from 1.2V supply. Measurement results show that the designed CTDSM achieves 92.6 dB SNDR and 94.1 dB DR over 40kHz bandwidth. The corresponding Schreier figure-of-merit is 177.3 dB.

This paper presents a behavior-level approach to improve the SQNR of incremental zoom ADCs with low hardware costs. The digital outputs of the L-th incremental zoom ΔΣ modulator are decimated using an (L+1)-th cascade-of-integrator (CoI) filter. The final quantization error is reduced through accumulating the original quantization error and then averaging. Moreover, the tonal component in the quantization error of zoom architectures is mitigated by injecting Gaussian dithering at the coarse SAR ADC input. Simulation results reveal that a dithered 2nd-order 5-bit incremental zoom ADC can achieve 114.5dB SQNR with a 3rd-order CoI decimation filter, showing a 7dB improvement over the architecture without this method. The resulting hardware overhead is only capacitors for dithering and DFFs in the digital filter, hardly raising any requirement for the analog circuit blocks.

This paper proposes a dual-mode AFE system that supports both voltage and electrochemical impedance spectroscopy (EIS) monitoring for multiple cell Li-ion batteries. The proposed current-balanced IA adapts the common mode voltage of the selected cell by taking the same voltage from the same cell, enabling multiple cell monitoring with minimum current. The system also includes a DC-servo loop cancelling the DC component from the AC voltage excited by a current generator. To the best of the author’s knowledge, it is the first BMS AFE system supporting multiple cell EIS monitoring, providing better SoC/SoH estimation and safety for Li-ion batteries.

This paper demonstrates the design of a high-resolution continuous-time (CT) incremental delta-sigma (I-$\Delta \Sigma $) analog-to-digital converter (ADC). A zero-order successive approximation register (SAR)-assisted extended counting is adopted to achieve higher resolution without affecting the thermal noise performance and conversion time. Acting like a 2-0 multi-stage noise-shaping (MASH) structure, achieving enhanced resolution and improved linearity with little power consumption is possible. Additionally, several energy-efficient techniques are adopted. Fabricated in 55-nm CMOS, the prototype occupies 0.36mm2 active area and consumes$188.6\mu $W from a 1.2-V supply. The implemented CT-IADC achieves a measured dynamic range (DR) of 96.5 dB and a signal-to-noise-and-distortion ratio (SNDR) of 95.4 dB for a maximum input of 1.9Vpp and a bandwidth of 20kHz. The measured SNDR-based Schreier figure of merit (FoM$_{\mathrm {S}}$) is 175.4 dB, the best among the reported results for CT-IADCs. It achieves a 5-dB FoMS improvement on the state-of-the-art works.

This article presents a two-stage pipelined noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converters (ADCs) for sub-micro-watt and high-resolution applications. However, it asks for an accurate residue amplification to avoid severe quantization noise leakage from the frontend stage. Therefore, a charge-efficient correlated-level-shifting (CECLS) assisted residue amplifier (RA) is designed by inserting the level-shifting network (LSN) in a two-stage floating inverter amplifier (FIA). In addition to the inherited low-power merit from FIA, it boosts the equivalent open-loop gain to 92 dB while preventing bandwidth reduction and charge-sharing effects, making the amplification more accurate and faster than prior CLS-assisted amplifiers. The prototype is fabricated using 55 nm CMOS technology and occupies an active area of 0.26 mm$^{\mathbf {2}}$. The measurement results show a 96.2 dB peak-SNDR and 871 nW power consumption under a 1.2 V supply voltage with a 16 kS/s sampling rate. Compared to the recent state-of-the-art ADCs with power under$10\mu $W and SNDR exceeding 90 dB, this ADC presents the best Schreier FoM of 180.8 dB.

A constant off-time (COFT) based current-balancing (CB) technique is proposed for integrated multi-phase DC-DC switching regulators with wide input/output (I/O) voltage range. The small-signal characteristics and design criteria of the proposed technique are derived based on describing functions. The current-balancing accuracy of the proposed technique depends merely on the ratio between the sensing FETs and the corresponding power switches ($\alpha $), while the requirement on absolute equivalent sensing-resistances ($R_{\mathrm {i}}$) and the matching of sensing circuits among phases are relaxed. Meanwhile, both the proposed current-balancing behavior and the adjustment of phase number will not affect the stability and the transient behavior of the multi-phase system. Furthermore, as a crucial block of the COFT control scheme, the proposed self-tuning PLLs of clock synchronization loop can remain fixed bandwidth under different I/O voltages, which further enhance the system stability. Therefore, in principle, the phase-interleaving with fixed switching frequency can be realized without the limit of duty cycle. As a result, the proposed CB technique can alleviate the stringent matching requirement of layout in conventional multi-phase systems, as well as the loop compensation difficulty. It is verified by an integrated dual-phase regulator fabricated in a$0.18\mu $m BCD process. Experimental results show that the regulator can provide 0.9-1.8V output from a 2.3-5.5V input at both steady state and load-transient state with significantly higher performance by the proposed CB technique, ensuring current-imbalance ratio within ±1.3%.

To achieve high efficiency over wide load range for modern mobile applications, this brief proposes a ripple-based V2-controlled buck converter operating with pulsewidth modulation (PWM)/pulse-frequency modulation (PFM)/load-adaptive standby mode (LASM). On system level, a delay-based load-adaptive V$_{\text {ON}}$generator is exploited in LASM at ultralight load. When the output ripple is kept below its maximum restriction, the switching loss of the converter is further minimized in LASM compared with prior operation modes, including PFM, pulse-skip modulation (PSM), multiple-sawtooth PWM (MSPWM), and deep green mode (DGM). On circuit level, a dynamic-biased dual-offset hysteresis comparator is proposed. Together with other blocks that can be disabled, the quiescent consumption of controller in LASM is reduced to only 14$\mu $W. Fabricated in a 130-nm BCD process, the proposed converter can provide a 1.8-V output with a power density of 4.11 W/mm2. It achieves a 93.2% peak efficiency, while the efficiency can be maintained above 86.4% in 1 mW–10 W ($\times 10~000$) load range.

This work proposes a floating-inverter-amplifier (FIA) based high-precision dynamic zoom ADC for low-voltage battery-powered applications. A capacitive biasing technique is proposed to reboot the FIA under low voltages, which enables the FIA to operate under a near-threshold supply voltage. Furthermore, correlated-level-shifting (CLS) is employed to boost the DC gain of the FIA to 51 dB. Simulated in 55nm CMOS under a 0.5V supply, the zoom ADC achieves 84.3dB SNDR while only consuming 723nW at a signal bandwidth of 1kHz. This corresponds to a state-of-the-art Schreier figure-of-merit (FoM) of 175.7 dB.

This paper presents a low-power chopper-stabilized capacitively-coupled frontend amplifier with auxiliary-path-based input impedance ( Z$_{\mathbf{in}}$) boosting. In order to achieve a high Z$_{\mathbf{in}}$, a low noise and a small chip area, techniques on both system level and circuit level are implemented. On the system level, small capacitors ( C$_{\mathbf{in}}$$=$0.5 pF, C$_{\mathbf{fb}}$$=$25 fF) are used with a biased pseudo-resistor ( R$=$2.5 G$\Omega $) fed back to an amplifier internal node. As a result, a high achievable Z$_{\mathbf{in}}$and low high-pass corner frequency are achieved. On the circuit level, an input capacitance shielded current feedback (CSCF) topology achieving effective 10 fF C$_{\mathbf{amp}}$is proposed as the core of the capacitive feedback amplifier in order not to increase the input noise. Moreover, the design space of auxiliary-path-based boosting is explored to obtain the optimal value of buffer bandwidth and auxiliary capacitor size to save power. The amplifier and its Z$_{\mathbf{in}}$boosting circuit are implemented in a standard 55 nm CMOS process and characterized experimentally. Measurement results show that the proposed amplifier provides an input noise density of 50 nV/$\surd$Hz, and an integrated noise of 0.85$\mu$V$_{\mathbf{rms}}$in 200 Hz band. The Z$_{\mathbf{in}}$is boosted to 1.92 G$\Omega $at DC and 1.02 G$\Omega $at 50 Hz with only 1.0$\mu$A in each auxiliary path buffer. The amplifier also archives 77 dB CMRR and 76 dB PSRR while consuming 20.3$\mu$W in total.

This paper presents a novel two-stage amplifier, which cascades a duty-cycled inverter-based OTA and a floating-inverter amplifier (FIA). The proposed OTA-FIA can achieve 72.0dB gain under a 1.2V supply, whose output swing is 420mV. Additionally, it exhibits intrinsic loop stability without compensation and reduces thermal noise during integration. The proposed OTA-FIA is adopted in a low distortion 1-1-1 MASH structure to obtain high resolution. Simulated in a 55 nm CMOS process, the proposed ADC can achieve an SNDR of 94.6dB with a bandwidth of 50kHz. It consumes$363.8\mu \mathrm{W}$from a 1.2V supply at a 5MS/s sampling frequency, resulting in a 176.0dB SNDR-based Schreier FoM.

A 1V 56.07dB SNDR 10MHz bandwidth digital slope ADC based on Preset Bidirectional-Shifting Technique is presented. With the proposed Preset Bidirectional-Shifting Technique, the number and conversion time are decreased impressively. Under low input frequency, the structure can achieve high resolution and high speed. Moreover, passive noise-shaping is used to implement an on-chip correction for the comparator latency. The proposed ADC is simulated in a 55nm CMOS process, achieving an SNDR of 56.07dB and consuming 941μW with a 1V supply. The simulation achieved a Schreier FoM of l56.33dB.

This paper presents a tri-mode buck converter with seamless mode transition. An auto-transition adaptive on-time generator is designed to realize the automatic transition between PWM and PFM modes. In order to achieve low quiescent current and high efficiency under ultra-light load, an ECO mode is proposed. An adaptive main comparator is presented with its bias current and feedback resistors dynamically adjustable to realize load-dependent seamless mode transition between PWM/PFM and ECO modes. The proposed tri-mode buck converter is implemented in 180nm CMOS process with 0.001 to 50mA (50000X) load range. The minimum quiescent current is 486nA and the maximum efficiency is 92%. Also, the efficiency remains over 85% from 0.1mA to 50mA.

Because it is magnet-free and can achieve a high integration level, the switched-capacitor (SC) converter acting as a direct current transformer has many promising applications in modern electronics. However, designing an SC converter with large current capability and high power efficiency is still challenging. This paper proposes a dual-branch SC voltage divider and presents its integrated circuit (IC) implementation. The designed SC converter is capable of driving large current load, thus widening the use of SC converters to high-power applications. This SC converter has a constant conversion ratio of 1/2 and its dual-branch interleaved operation ensures a continuous input current. An effective on-chip gate-driving method using a capacitively coupled floating-voltage level shifter is proposed to drive the all-NMOS power train. Due to the self-powered structure, the flying capacitor itself is also a bootstrap capacitor for gate driving and thus reduces the number of needed components. A digital frequency modulation method is adopted and the switching frequency decreases automatically at light load to improve light load efficiency. The converter IC is implemented using a 180 nm triple-well BCD process. Experimental results verify the effectiveness of the dual-branch interleaved operation and the self-powered gate-driving method. The proposed SC divider can drive up to 4 A load current with 5–12 V input voltage and its power efficiency is as high as 96.5%. At light load, using the proposed optimization method, the power efficiency is improved by 30%.

An ultra-low quiescent current tri-mode DC-DC buck converter is presented in this paper, which is able to handle a 100,000X load range. In pulse width modulation (PWM) and pulse frequency modulation (PFM) mode, adaptive on-time (AOT) V2control is utilized to achieve seamless mode transition and constant switching frequency in PWM mode. A deep green mode (DGM) is proposed for light load, where both the switching loss and the power of control circuitry are minimized. By reducing the comparator current, a delay-based hysteresis window adaptive to load current is generated, reducing the switching frequency and the loss. Meanwhile, the average current of zero current detector (ZCD) and AOT controller are reduced significantly by dynamic biasing. As a result, the efficiency of the converter is improved while maintaining a reasonable output ripple. The proposed converter is implemented in a$0.18\mu $m BCD technology. Experimental results show that the converter can provide a 1.6 V output from a 2.7 to 4.7V input for$1\mu $A to 100 mA load, while consuming only 490nA quiescent current. The proposed converter achieves a 92.1% peak efficiency and efficiency can be maintained above 80% in a load range of$20\mu $A to 60 mA.

Reliable and timely seizure prediction has been increasingly helpful and indispensable for epileptic patients, ensuring safety and improving life quality. Based on electroencephalogram (EEG), a new patient-specific seizure prediction method is proposed in this paper to detect impending seizures automatically and accurately, using a novel indicator called maximum synchronization modularity. As the first step towards this goal, raw EEG signals are decomposed by multivariate empirical mode decomposition (MEMD). Then graph community detection algorithm is applied to characterize the phase synchronization modularity of sub-band EEG signals. Thus, the deep interaction of scalp electrical activity can be effectively revealed. Finally, radial basis function neural network (RBFNN) is used for the classification. The proposed method achieves an average prediction accuracy of 99.06% and an average sensitivity of 100% on CHB-MIT scalp EEG database, outperforming related works based on the same database.

The paper presents an external capacitorless low-dropout regulator (LDO) with a ultra-low quiescent current for system-on-chip (SoC) in portable electronic applications. A sub-1-V, nanopower voltage reference ensures the low power consumption of the LDO system. The external capacitorless design allows the LDO to be fully integrated on chip, which not only saves area and cost, but also eliminates bond-wire effects. In order to compensate the lack of large off-chip output capacitor, a two-stage error amplifier with nested Miller compensation is applied to ensure system stability. Besides, a small on-chip output capacitor and a slew-rate enhancement circuit are attached to improve transient response. The proposed LDO is designed and simulated in 55 nm process. Compared with prior works, this LDO has the minimum output capacitor of 5pF and the ultra-low quiescent current of 2.3μA with load regulation of 0.41mV/mA and figure-of-merit (FOM) of 1.95.

A high efficiency 1/2X switched capacitor (SC) DC-DC converter capable of providing high load current up to 10 A is presented in this paper. To maintain high efficiency over the wide load range, adaptive switching frequency is adopted. By modeling the output impedance and power loss of the SC converter, the influence of switching frequency on efficiency is quantified to find the optimal switching frequency at each load. Linear frequency modulation is built since the optimal switching frequency is proved to be proportional to the load. Subtractor with high bandwidth and automatic frequency modulation module are proposed to ensure the converter work at the optimal frequency under each load. Using 0.18μm BCD process, simulation results show the proposed SC converter can quickly adjust the switching frequency during load transients. Over 86% efficiency is achieved over the entire load range from 5 mA to 10 A and peak efficiency is higher than 98%. Meanwhile, the output voltage ripple is guaranteed less than 40 mV.

Depth image-based rendering (DIBR) techniques have recently drawn more attention in various 3D applications. In this paper, a real-time high-quality DIBR system that consists of disparity estimation and view synthesis is proposed. For disparity estimation, a local approach that focuses on depth discontinuities and disparity smoothness is presented to improve the disparity accuracy. For view synthesis, a method that contains view interpolation and extrapolation is proposed to render high-quality virtual views. Moreover, the system is designed with an optimized parallelism scheme to achieve a high throughput, and can be scaled up easily. It is implemented on an Altera Stratix IV FPGA at a processing speed of 45 frames per second for 1080p resolution. Evaluated on selected image sets of the Middlebury benchmark, the average error rate of the disparity maps is 6.02%; the average peak signal to noise ratio and structural similarity values of the virtual views are 30.07 dB and 0.9303, respectively. The experimental results indicate that the proposed DIBR system has the top-performing processing speed and its accuracy performance is among the best of state-of-the-art hardware implementations.

With the development of application processors in mobile device, the power supply is required to have high current driving capability and low standby power consumption. In this paper, a novel dual-phase DC-DC buck converter with low quiescent consumption is proposed to meet the demand. Apart from conventional PWM/PFM mixed control, an extra power-save mode (PSM) is designed in the converter to minimize the power consumption at extremely light load. The converter is designed, simulated and fabricated in 0.18 μm Global Foundry BCD technology. The experimental results show that the chip could provide maximum output current of 6 A. With PSM, the current consumption of the chip was reduced by up to 96% under light load condition and the standby quiescent current was 6 μA.

This paper presents a capacitively-coupled chopper instrumentation amplifier (CCIA) for portable EEG detection devices. In this design, the current-reuse technology is adopted in the core amplifier and the ripple reduction loop (RRL) to cut down the power consumption of the whole system. A novel ripple reduction loop based on ping-pong auto-zeroing topology is proposed to reduce the ripple at the output of the CCIA. It makes the chopping ripple be attenuated about 46 dB. This system is simulated in a 0.18 μm CMOS process. Simulation results show that the proposed CCIA achieves an equivalent input noise power spectrum density (PSD) of 32 nV/VHz, a noise efficiency factor (NEF) of 1.7, CMRR of 90 dB. The overall current consumption is 1.8 μΑ at a 1V supply.

In this paper, an universal LED driver that adaptive to both buck and boost topologies with high dimming ratio is proposed based on energy harvesting system. The proposed driver can realize either step-up or step-down functions, depending on the connection with power stage. Moreover, PWM dimming is achieved to adjust the brightness to enhance battery life. The proposed controller is designed and fabricated in 1.5μm BCD process and experimental results verify the design under different topologies. The maximum dimming ratio reaches 3000:1 at 100Hz dimming frequency.

A high efficiency high dimming ratio boost LED driver without color shift issue is presented in this paper. The boost converter is controlled by an adaptive on-time (AOT) controller, using improved control stratagem based on constant on-time (COT) control, so as to realize fast transient response to achieve high dimming ratio. With AOT control, the operation frequency maintains constant under continuous current mode (CCM) and the output voltage ripple could be reduced. In addition, Pulse frequency modulation (PFM) is implemented automatically under discontinuous current mode (DCM) to improve the system efficiency. The chip was designed and implemented in 1.5 μm bipolar-CMOS-DMOS (BCD) process. The simulation and experimental results showed that the minimum dimming on-time could be reduced to 1.2 μs, which means a dimming ratio of 2000:1 is available at dimming frequency of 400 Hz.

A low power high performance Delta-Sigma modulator for portable measurement applications is presented. To reduce power consumption while maintaining high performance, a fully feedforward architecture with a comprehensive system-level design is implemented. As a key building block, a novel power efficient current mirror operational transconductance amplifier (OTA) with a fast-settling less-error switched-capacitor common-mode feedback (SC CMFB) circuit is introduced, and the effects of both gain nonlinearity and 1/ f noise of OTA are discussed. A new method to determine the voltage gain of an OTA is also proposed. The bottom terminal parasitic effect of poly-insulator-poly (PIP) capacitors is considered. About an extra 20% of capacitance is added to the total capacitance load. A power and area efficient resonator is adopted to realize a coefficient of 1/90 for 50% power and 75% area reduction compared with conventional designs. The chip is implemented in a low cost 0.35 μm complementary metal oxide semiconductor (CMOS) process. The total power consumption is 20 μW with a 1.5 V supply, and the measured dynamic range (DR) is 95 dB over a 1 kHz bandwidth. Experimental results show that a high figure-of-merit (FOM) is achieved for the designed modulator in comparison with those from the literature.