EDBT 2026 Demo / reviewers in the wild / expert
Zhu Pan
dblp:65/5383
· DBLP profile ↗
7ranked-venue papers
0as first author
2since 2021 · last 2021
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Software maintenance and evolution · 87% Empirical software engineering · 13% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 87% Integrated circuit design · 13% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Software maintenance and evolution
log analysis |
0.5 | 1 | 2021 | An empirical investigation of practical log anomaly detection for online service systems · ESEC/SIGSOFT FSE 2021 |
Software maintenance and evolution › log analysis
log-based anomaly detection |
0.5 | 1 | 2021 | An empirical investigation of practical log anomaly detection for online service systems · ESEC/SIGSOFT FSE 2021 |
Empirical software engineering
mining software repositories |
0.1 | 1 | 2021 | An empirical investigation of practical log anomaly detection for online service systems · ESEC/SIGSOFT FSE 2021 |
Electronic design automation
circuit simulation |
0.1 | 1 | 2006 | Time-domain analysis methodology for large-scale RLC circuits and its applications · Sci. China Ser. F Inf. Sci. 2006 |
Electronic design automation › circuit simulation
transient analysis |
0.1 | 1 | 2006 | Time-domain analysis methodology for large-scale RLC circuits and its applications · Sci. China Ser. F Inf. Sci. 2006 |
Integrated circuit design › analog and mixed-signal circuits
RLC circuits |
0.0 | 1 | 2006 | Time-domain analysis methodology for large-scale RLC circuits and its applications · Sci. China Ser. F Inf. Sci. 2006 |
Methods — techniques the papers use, named apart from their topics
ensemble learning · 0.5domain knowledge integration · 0.5anomaly detection · 0.5time-domain analysis · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | An Improved Constant Modulus Algorithm and Its Generalized Form for Blind EqualizationabstractIn wireless communication systems, the conventional constant modulus algorithm incurs artificial error and steady state misadjustment. In this study, an improved constant modulus algorithm (ICMA) and its generalized form are proposed for blind equalization. The ICMA utilizes the clustering function of Gaussian function to efficiently suppress this artificial error and steady state misadjustment at the cost of reduction in the sample usage rate. Moreover, the generalized form of the ICMA is developed to ensure the sample usage rate while the good performances of the ICMA are maintained. Simulation results illustrate better equalization performances of the ICMA and generalized ICMA, as compared to the classical constant modulus algorithm. Wei Xing Zheng 0001, Da-Zheng Feng, Zhu Pan, Jin Li 0016 |
ISCAS | 3 |
| 2021 | An empirical investigation of practical log anomaly detection for online service systemsabstractLog data is an essential and valuable resource of online service systems, which records detailed information of system running status and user behavior. Log anomaly detection is vital for service reliability engineering, which has been extensively studied. However, we find that existing approaches suffer from several limitations when deploying them into practice, including 1) inability to deal with various logs and complex log abnormal patterns; 2) poor interpretability; 3) lack of domain knowledge. To help understand these practical challenges and investigate the practical performance of existing work quantitatively, we conduct the first empirical study and an experimental study based on large-scale real-world data. We find that logs with rich information indeed exhibit diverse abnormal patterns (e.g., keywords, template count, template sequence, variable value, and variable distribution). However, existing approaches fail to tackle such complex abnormal patterns, producing unsatisfactory performance. Motivated by obtained findings, we propose a generic log anomaly detection system named LogAD based on ensemble learning, which integrates multiple anomaly detection approaches and domain knowledge, so as to handle complex situations in practice. About the effectiveness of LogAD, the average F1-score achieves 0.83, outperforming all baselines. Besides, we also share some success cases and lessons learned during our study. To our best knowledge, we are the first to investigate practical log anomaly detection in the real world deeply. Our work is helpful for practitioners and researchers to apply log anomaly detection to practice to enhance service reliability. Nengwen Zhao, Honglin Wang, Zeyan Li 0001, Zhu Pan, Xidao Wen, Wenchi Zhang, Kaixin Sui, Dan Pei |
ESEC/SIGSOFT FSE | 6 |
| 2008 | Large scale P/G grid transient simulation using hierarchical relaxed approach
Yici Cai, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan |
Integr. | 3 |
| 2006 | Time-domain analysis methodology for large-scale RLC circuits and its applications
Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Zhu Pan, Jingjing Fu |
Sci. China Ser. F Inf. Sci. | 6 |
| 2005 | Relaxed hierarchical power/ground grid analysisabstractThis paper proposes a novel hierarchical approach to the efficient analysis of large VLSI power/ground grids. Different from the existing hierarchical approach where sub-circuit equivalent models are sparsified with computation-intensive integer programming and the resulting modeling may lead to larger errors if the top circuit matrix has large condition number, the new approach employs an iterative (relaxation) procedure to explicitly compensate the errors and avoid introducing dense matrix caused by the circuit reduction. We also propose an efficient scheme for partitioning high performance center-bumped P/G grids. Experimental results demonstrate that the new algorithm is more accurate than the existing hierarchical method while delivering more speedup over the flat simulators. Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu 0002 |
ASP-DAC | 2 |
| 2005 | VLSI on-chip power/ground network optimization considering decap leakage currentsabstractIn today's power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leakage current becomes worse as the gate oxide layer thickness continues to shrink below 20Å. As a result, decaps will become leaky due to the gate leakage from CMOS devices. In this paper, we take a first look at the leaky decaps in P/G network optimization. We propose a leakage current model for practical decaps and also present a new two-stage leakage-current-aware approach to efficiently optimize P/G networks in a more area efficient way. Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan |
ASP-DAC | 6 |
| 2004 | A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan |
ASP-DAC | 6 |