This paper presents an ultra-low power low-dropout (LDO) regulator that employs three adaptive enhancements to dynamically optimize efficiency and performance across load conditions. Implemented in a GlobalFoundries 55 nm CMOS process and occupying 0.076 mm2, the regulator delivers 1.2V from a 1.8V supply, with functionality down to 1.37V. An adaptive gain boost (AGB) provides up to 25.2dB improvement in loop gain and more than 20 dB power-supply rejection ratio (PSRR) enhancement at high load. Adaptive Miller compensation (AMC) and adaptive headroom extension (AHE) expand the effective load range to 15 mA and extend the bandwidth by$2.5\times $to247.3kHz. The LDO achieves a quiescent current of 827 nA, sustaining >90% current efficiency at$10~\mu $A load and >99% at 15 mA, with stable operation in both capacitor-free and capacitor-loaded modes. Measured results across five chips and 200-run Monte Carlo simulations confirm robustness to variability. By combining ultra-low quiescent current, wide load scalability, and adaptive rejection, the proposed LDO provides a practical solution for duty-cycled biosensing and IoT systems requiring high efficiency during idle operation and strong performance under active load.

This paper describes a 4-channel phase detector based inductive sensing IC targeted at mobile device mechanical button replacement. Salient features include active-drive TX with low EMI sensitivity (<10mV differential drive), interference robustness and scalable performance. First silicon achieves an industry leading combination of performance (0.1μm displacement sensitivity) and power (124μW @100 Hz scan rate). Keywords— Sensors, Inductive Sensing, Resonant Phase Sensing, Mechanical/Virtual Buttons, I/Q Demodulation.

We present a novel hardware trojan that entirely originates and subverts in the analog domain. In the context of a System-on-a-chip (SoC) or System-in-a-package (SiP), it can compromise the system without any crossover or interaction with the digital subsystem, rendering it undetectable by existing digital detection methods. Potential adversaries include an untrusted designer, IP vendor, or system integrator. The trojan attacks via a temporal excursion applied on the power supply of the system. It is expressive at multiple levels, at the control of the attacker. It can be built entirely from existing analog dummy structures and incurs very low power and area overheads. We evaluate this trojan on an electrocardiogram (ECG) biometric analog front-end and demonstrate its ability, expressiveness, stealthiness, and controllability. It can cause false authentication and corruption of biometric data while remaining undetected by current analog test methodologies. Through this work, we highlight the critical need for development of detection strategies directly focused on such analog trojans.

We present a memristor-based delay cell design for time-domain neuromorphic computing inference. Each cell computes partial dot product operations using current summation, and multiple cells chained together complete the computation by accumulating their delays. The design is analyzed over process, voltage, and temperature variations to gain insight into the impact of the cell size (number of inputs) on performance and robustness. Results based on a 64-input neuron show that, while smaller cell sizes have better dynamic range (> 5), larger cells have significantly reduced delay (≈ 25), power× consumption (≈ 8×), and transistor count (≈ 3×). We× also find that there is a strong dependence between cell size and variability at reduced power supply voltage. Along with our analyses, we provide a detailed discussion of these tradeoffs to help designers choose the optimal configuration for their applications.

Increasing process variations and tolerance limits with successive scaling, along with rising costs per design cycle have made the fault-tolerance paradigm pertinent in RFICs. Due to the high frequencies involved, traditional fault-tolerance methods used in digital and lower frequency analog circuits cannot be applied. This paper presents a non-intrusive and robust technique of self-calibrating the gain and output match of LNAs. It involves very low overheads and does not degrade circuit performance in any measurable way, in addition to ultra-fast calibration times (lower than 50 mus). We present simulation results of the system designed in the IBM 0.25 mum process