EDBT 2026 Demo / reviewers in the wild / expert

Nasser Shayesteh

dblp:65/6416 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 44% Reconfigurable computing and FPGAs · 44% Processor architecture and microarchitecture · 13%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
hardware verification		 0.011995
UltraSPARC-I Emulation · DAC 1995
Reconfigurable computing and FPGAs
processor emulation		 0.011995
UltraSPARC-I Emulation · DAC 1995

Methods — techniques the papers use, named apart from their topics

emulation · 0.0
YearPublicationVenuePosition
1995 UltraSPARC-I Emulation
abstract
The next generation UltraSPARC-I CPU represents a significant step forward in processor performance at the cost of increased design complexity.Added complexity increases the risks in achieving functionally correct first silicon.Existing design verification techniques were supplemented by applying emulation to obtain an early look at functionality.Discussed are the goals, methods and results of the UltraSPARC-I emulation.
James Gateley, Miriam Blatt, Dennis Chen, Scott Cooke, Piyush Desai, Manjunath Doreswamy, Mark Elgood, Gary Feierbach, Tim Goldsbury, Dale Greenley, Raju Joshi, Mike Khosraviani, Robert Kwong, Manish Motwani, Chitresh Narasimhaiah, Sam J. Nicolino Jr., Tooru Ozeki, Gary Peterson, Chris Salzmann, Nasser Shayesteh, Jeffrey Whitman, Pak Wong
 DAC20