This paper presents a flexible architecture suitable for concurrent processing of multiple radio standards. The proposed architecture is based on a coarse-grained reconfigurable cell array, consisting of distinct processing and memory cells. Flexibility of the architecture is demonstrated by performing a coarse time synchronization and fractional frequency offset estimation for multiple OFDM standards. The radio standards under analysis are IEEE 802.11n, LTE, and DVB-H. The reconfigurable cell array, containing 2-by-2 cells, is capable of processing two concurrent data streams from the standards. Dynamic reconfigurability of the architecture enables run-time switching between the standards. The implemented 2-by-2 cell array is synthesized using a 65 nm low-leakage standard cell CMOS library, resulting in an area of 0.479mm2and a maximum clock frequency of 534MHz. High flexibility offered by the reconfigurable cell array allows the adoption of different algorithms onto the same platform.

This paper intends to provide a techno-economic overview of the Mobile TV business and its business models. Recent trials have shown that a large number of people would like to consume mobile TV and few people doubt that this service will eventually be offered in the majority of wireless networks around the world. However, this service is not a simple add-on to the voice and data, but comes with totally new dimensions that challenge the present markets. The aim of this paper is to identify and describe these challenges in the technology, market behaviour, and industry strategy domains.

In this paper we discuss how communication systems can be designed considering requirements focusing on the end-user services and the business environment and business logic. We target business users using services supporting work in mobile environments with a temporary project organization. The discussion and analysis will be based on findings from construction projects. These projects are usually temporary, highly mobile and geographically distributed business organizations with common work processes that require close interaction between multiple users and business partners. The analysis starts with characterization of user behaviour, user environments and project organizations. Communication and mobility in construction projects are described and possible services and business roles are proposed. Examples of candidates to take these business roles are discussed based on capabilities and incentives of these companies.

In this paper we discuss how communication systems can be designed considering requirements focusing on the end-user services and the business environment and business logic. We target business users using services supporting work in mobile environments with a temporary project organization. The discussion and analysis will be based on findings from construction projects. These projects are usually temporary, highly mobile and geographically distributed business organizations with common work processes that require close interaction between multiple users and business partners. The analysis starts with characterization of user behaviour, user environments and project organizations. Communication and mobility in construction projects are described and possible services and business roles are proposed. Examples of candidates to take these business roles are discussed based on capabilities and incentives of these companies.

A runtime system for implementation of image processing operations is presented. It is designed for working in a flexible and distributed environment related to the software architecture of a newly developed UAV system. The software architecture can be characterized at a coarse scale as a layered system, with a deliberative layer at the top, a reactive layer in the middle, and a processing layer at the bottom. At a finer scale each of the three levels is decomposed into sets of modules which communicate using CORBA, allowing system development and deployment on the UAV to be made in a highly flexible way. Image processing takes place in a dedicated module located in the process layer, and is the main focus of the paper. This module has been designed as a runtime system for data flow graphs, allowing various processing operations to be created online and on demand by the higher levels of the system. The runtime system is implemented in Java, which allows development and deployment to be made on a wide range of hardware/software configurations. Optimizations for particular hardware platforms have been made using Java's native interface.

Java has proven to be a powerful language for software development. In this paper we show that it is also suitable for hardware compilation, making it an attractive language for embedded system development. Our compilation technique, which is presented here, is based on separating different aspects of the program and use dedicated and specialised optimisations and code generators for each aspect. In this paper we focus on efficient implementation of random memory accesses, i.e. reference intensive tasks, such as graph traversal. We show that for these tasks the hardware generated by our compiler is up to 1.8 times faster than a software implementation. We also show how recursive algorithms can be mapped to hardware using our tool.

Recently substantial research has been devoted to Unmanned Aerial Vehicles (UAVs). One of a UAV's most demanding subsystem is vision. The vision subsystem must dynamically combine different algorithms as the UAVs goal and surrounding change. To fully utilize the available hardware, a run time system must be able to vary the quality and the size of regions the algorithms are applied to, as the number of image processing tasks changes. To allow this the run time system and the underlying computational model must be integrated. In this paper we present a computational model suitable for integration with a run time system. The computational model is called Image Processing Data Flow Graph (IP-DFG). IP-DFG has been developed for modeling of complex image processing algorithms. IP-DFG is based on data flow graphs, but has been extended with hierarchy and new rules for token consumption, which makes the computational model more flexible and more suitable for human interaction. In this paper we also show that IP-DFGs are suitable for modelling expressions, including data dependent decisions and iterations, which are common in complex image processing algorithms.

There are many important factors to consider when designing a network interface for an ATM network, and different applications have different demands. This paper addresses the problem of making an ATM interface with the focus on very low message latency, e.g., for shared memory multiprocessors on top of a network of workstations, and yet making it general enough to be a cost effective solution. Different approaches to the interface are evaluated and an architecture where critical functions are distributed and performed in dedicated hardware, integrated with, or very close to, the processors, are proposed.

Conditional sum adders, CSAs, and carry-lookahead adders, CLAs, both have logarithmic gate depth. However, CLAs require a final add stage while CSAs produce the sum bits in parallel with the final carry bit. For CMOS implementations, the depth advantage of CSA has been difficult to exploit since the traditional structure of CSAs have some heavily loaded internal nodes. We show that the CSA-operation forms a monoid and that all circuit structures, corresponding to parallel prefix algorithms, used with CLA to reduce internal fan-out, are applicable also to CSAs. Furthermore, we show that all time critical computations in a CSA can be performed with monotone functions which allow efficient dynamic CMOS logic to be used. Finally we evaluate a variety of transistor level adder implementations with respect to speed and we show that in almost all cases the CSA has lower delay than its CLA counterpart.>

An interactive graphical editor for parameterized layout generators, based on symbolic layout, is discussed. One basic idea is to have built-in rules, corresponding to basic knowledge about elementary things in VLSI design, in order to make the tool behave as an experienced partner to the designer. It was found that the fundamental problem was not to implement but to select a proper set of rules to define the semantics of the tool. The problem was attacked by actually implementing various experimental versions and using them to create layout. These experiments and the conclusions are summarized. For example, the fundamental importance of proper mechanisms to explicitly express geometrical constraints, such as pitch-matching, is shown. It is also shown how parameterization can be introduced in a user-friendly and natural way through the graphical, symbolic layout view.>

BBDS, an interactive graphical design tool for developing clock cycle true system models, is described. A design idea is entered through graphical interaction based on the Werner diagram. All important decisions about scheduling and allocation of operations are visually explicit. The design can rapidly be verified through simulation, timing analysis, area estimation and prototyping in programmable gate arrays. This allows very fast evaluation of an architectural idea, and allows for a series of fast iterative design improvements, BBDS also enforces a set of formally defined rules based on attributes of signals and component connectors to guarantee consistency of the clocking scheme. Both standard components and software can be accommodated. BBDS can be used to investigate the partitioning of a computer system into software and hardware, and is based on automatic synthesis with a user selectable target library.>

An environment for silicon compilation tools in which module generators can be created, maintained, and operated on is defined. A module is defined by its specification, which can be hierarchically parameterized. Instantiation is based on a set of built-in rules including geometrical design rules and composition rules for modules. An abstraction of the functionality is created by defining a formal representation language and a set of operations on descriptions expressed in that language. The representation language is defined in such a way that all descriptions can be represented in two different domains, graphically on the screen and internally in a database. The set of operations can be expressed in both domains. The main advantage of introducing the language is that the functionality of the system can be described in a compact way on an abstraction level much higher than the implementation. The representation language explicitly represents geometrical connectivity and symbolic layout and is used for specifications and instances. Conditional and repetitive layout and regular arrays of modules are supported by the language. Specific support for compaction and routing tools is included.>

Movie is a special-purpose environment for silicon compilation tools, providing services in the same way that an operating system does to application problems. Movie also contains the functionality of an advanced module generator tool. An internal design representation was developed that allows a combination of hierarchically parameterized module generators, symbolic layout, and interactive graphical editing. This design representation has been formalized into a representation language with well-defined semantics. Movie provides a set of operations, formally defined using the representation language, for use by the tools. A set of instantiation mechanisms ensure certain correctness of the result independently of the tools and closes the design-verification loop. Movie was designed to take advantage of fast color graphics, special-purpose data structures and incremental updating to achieve interactivity with immediate visual feedback by real-time animation. By integration high-level tools, a hierarchy of levels of abstraction is maintained. Silicon compilation systems based on Movie can be expected to be open-ended, transparent, and highly interactive.>