Hoon Ryu

EDBT 2026 Demo / reviewers in the wild / expert

dblp:65/7209 · DBLP profile ↗

← Back

10ranked-venue papers

3as first author

4since 2021 · last 2025

—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 9 · 3 first-author · 3 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021

Year	Publication	Venue	Position
2025	Trade-offs in Virtual Grasping: The Interplay of Interaction Fidelity and Object Affordance abstract In Virtual Reality (VR), object grasping is a core interaction that critically influences both user immersion and task performance. While contemporary systems offer both high-precision controllers and intuitive hand tracking, they present a trade-off between performance and naturalness. However, empirical guidance for selecting an optimal grasping method for object grasping remains limited. In particular, how object shape and size (as affordance-related factors) modulate this trade-off within a standardized pick-and-place paradigm is underexplored. Jemin Lee 0001, Hyeongjun Kang, Hoon Ryu, Youngwon Kim	VRST	4
2024	Quantum-centric supercomputing for materials science: A perspective on challenges and future directions Yuri Alexeev, Maximilian Amsler, Marco Antonio Barroca, Sanzio Bassini, Torey Battelle, Daan Camps, David Casanova, Young Jay Choi, Fred Chong, Charles Chung, Christopher Codella, Antonio D. Córcoles, James Cruise, Alberto Di Meglio, Ivan Duran, Thomas Eckl, Sophia E. Economou, Stephan J. Eidenbenz, Bruce Elmegreen, Clyde Fare, Ismael Faro, Cristina Sanz Fernández, Rodrigo Neumann Barros Ferreira, Keisuke Fuji, Bryce Fuller, Laura Gagliardi, Giulia Galli, Jennifer R. Glick, Isacco Gobbi, Pranav Gokhale, Salvador de la Puente Gonzalez, Johannes Greiner, William Gropp, Michele Grossi, Emanuel Gull, Burns Healy, Matthew R. Hermes, Benchen Huang, Travis S. Humble, Nobuyasu Ito, Artur F. Izmaylov, Ali Javadi-Abhari, Douglas M. Jennewein, Shantenu Jha, Bert de Jong, Petar Jurcevic, William M. Kirby, Stefan Kister, Masahiro Kitagawa, Joel Klassen, Katherine Klymko, Kwangwon Koh, Masaaki Kondo, Doga Murat Kürkçüoglu, Krzysztof Kurowski, Teodoro Laino, Ryan Landfield, Matthew L. Leininger, Vicente Leyton-Ortega, Ang Li 0006, Meifeng Lin, Junyu Liu, Nicolás Lorente, André Luckow, Simon Martiel, Francisco Martín-Fernández, Margaret Martonosi, Claire Marvinney, Arcesio Castañeda Medina, Dirk Merten, Antonio Mezzacapo, Kristel Michielsen, Abhishek Mitra, Tushar Mittal, Kyungsun Moon, Joel Moore, Sarah Mostame, Mario Motta, Young-Hye Na, Yunseong Nam, Prineha Narang, Yu-ya Ohnishi, Daniele Ottaviani, Matthew Otten, Scott Pakin, Vincent R. Pascuzzi, Edwin Pednault, Tomasz Piontek, Jed W. Pitera, Patrick Rall, Gokul Subramanian Ravi, Niall Robertson, Matteo A. C. Rossi, Piotr Rydlichowski, Hoon Ryu, Georgy Samsonidze, Mitsuhisa Sato, Nishant Saurabh, Kunal Sharma, Soyoung Shin, George Slessman, Mathias Steiner, Iskandar Sitdikov, In-Saeng Suh, Eric D. Switzer, Joel Thompson, Synge Todo, Minh C. Tran, Dimitar Trenev, Christian Trott, Huan-Hsin Tseng, Norm M. Tubman, Esin Tureci, David García Valiñas, Sofia Vallecorsa, Christopher Wever, Konrad W. Wojciechowski, Xiaodi Wu 0001, Shinjae Yoo, Nobuyuki Yoshioka, Victor Wen-zhe Yu, Seiji Yunoki, Sergiy Zhuk, Dmitry Zubarev	Future Gener. Comput. Syst.	97
2022	Empirical Study on the GPU-accelerated HPL Performance: Effects of PCIe Communication abstract Computing resources equipped with GPU devices are popularly adopted in various application areas, and the HPL benchmark is used to evaluate their standard performance. The performance of GPU-accelerated HPL however cannot be free from PCIe communication even in the most optimal case. Here, we investigate the PCIe communication overhead and its effect on the NVIDIA HPL performance using a simple model. This preliminary study intends to derive a way that can estimate the HPL performance in upcoming computing resources that support full cache coherence between CPU and GPU memory. Jieun Choi, Yosang Jeong, Ji Hoon Kang 0002, Gibeom Gu, Hoon Ryu	CLUSTER	5
2021	High-performance simulations of turbulent boundary layer flow using Intel Xeon Phi many-core processors Ji Hoon Kang 0002, Jinyul Hwang, Hyung Jin Sung, Hoon Ryu	J. Supercomput.	4
2020	An HPC-based Prediction on the Practicality of Long-distance Quantum Key Distributions abstract Practicality of long-distance quantum communications based on a BB84 quantum key distribution (QKD) protocol is examined with Monte Carlo simulations coupled to a parallel computing. Given a quantum channel that is not free from noises, optimal sizes of the shared key information and corresponding chances for detecting the eavesdropper are calculated to present clues that can be utilized to figure out the utility of the protocol. Delivering simple but sound principles that have not been focused quite well, this work serves as a useful case study that shows the need of high performance computing for QKD modeling, and can trigger potential efforts for further modeling studies that involve more realistic and complicated factors. Hoon Ryu, Ji Hoon Kang 0002	CLUSTER	1
2019	Cost-efficiency of Large-scale Electronic Structure Simulations with Intel Xeon Phi Processors abstract Benefits of Intel Xeon Phi Knights Landing (KNL) systems in computing cost are studied with tight-binding simulations of large-scale electronic structures that involve sparse system matrices whose dimensions normally reach several tens of millions. Speed and energy usage of our in-house Schrödinger equation solver are benchmarked in KNL systems for realistic modelling tasks, and are discussed against the cost required by offload computing with P100 devices. Superiority in speed and energy-efficiency observed in KNL systems justify the practicality of bootable manycore processors that are adopted by nearly 30% of largest supercomputers in the world. With a demonstration of the strong scalability up to 2,500 nodes, this work serves as an useful case study that supports the utility of KNL systems for handling memory-bound applications including ours and other numerical problems that involve large-scale sparse matrix-vector multiplications, particularly compared to GPU-based systems. Hoon Ryu	CLUSTER	1
2017	Acceleration of Turbulent Flow Simulations with Intel Xeon Phi(TM) Manycore Processors abstract Enhancing the performance of turbulent flow simulations is important as the size of simulations grows with higher Reynolds number. We discuss the performance of our in-house turbulent flow simulation solver, named as DNS-TBL (Direct Numerical Simulation: Turbulent Boundary Layer), on the Intel Xeon Phi™ manycore processors. With bootable Knights Landing processors, the DNS-TBL solver shows excellent parallel scalability and, in particular, shows a 1.6 times better performance in solver time than the original CPU-based version. Current intermediate results serve as a practical case-study which directly shows how much turbulent flow simulations can be accelerated on manycore processors, providing a good reference for the parallelization and optimization schemes in the filed of computational fluid dynamics. Ji Hoon Kang 0002, Hoon Ryu	CLUSTER	2
2017	Performance of Large-Scale Electronic Structure Calculations on Built-in FPGA Systems abstract We discuss the feasibility of an in-house Schrödinger equation solver on the Intel Broadwell Xeon processor with a built-in FPGA, with a particular focus on the performance of large-scale sparse matrix-vector multiplication (SpMV) that is the core numerical operation of electronic structure simulations for multi-million atomic systems. The double-precision SpMV section in our solver is offloaded to FPGA using OpenCL SDK tool chain presented by Intel corporation. Memory-pinning and duplication of compute unit are employed to improve the performance, where we find that memory-pinning and duplication of compute units lead 1.64x faster data-transfer and 1.58x speed-up of SpMV, respectively, against the result with a single compute unit and no pinned memory. Dukyun Nam, Hoon Ryu	CLUSTER	3
2016	EDISON: A Web-Based HPC Simulation Execution Framework for Large-Scale Scientific Computing Software abstract Computational science and engineering (CSE) researchers usually develop their own technology computer-aided design (TCAD) programs, accompanying large-scale computation and I/O on high-performance computing (HPC) resources like clusters or supercomputers. The researchers typically use command-line interface (CLI) such as Terminal to access the HPC resources. But CLI may not be a useful tool to those who conduct research or get educated with the TCAD software, because of their unfamiliarity with executing a series of commands. Thus there has been a strong need on a platform that assists domain-specific scientists to easily share, access, and run TCAD services. To satisfy the need, in this poster we present a novel cyber-environment, called "Education-research Integration through Simulation On the Net" (EDISON), which has been designed and implemented to access and run various TCAD software tools developed in five selected CSE fields over the past four years. The EDISON platform comprises three layers: application portal to browse and run TCAD software, middleware to manage metadata associated with TCAD software and handle online simulation jobs, and infrastructure to support network, storage, and computing resources. In this demo a user will interact with the EDISON platform to perform two representative use-case scenarios: 1) browsing various TCAD tools, selecting one of the tools, controlling with its parameters, and running a simulation job from the tool, and 2) constructing a scientific workflow of selected TCAD tools and executing the workflow. At the end, the user will visualize the completed simulation results. Young-Kyoon Suh, Hoon Ryu, Hangi Kim, Kumwon Cho	CCGrid	2
2016	Enhancing Performance of Large-Scale Electronic Structure Calculations with Many-Core Computing abstract Time-efficient computation of large-scale sparse matrices is important in many areas of computational science. The performance of an in-house Schrödinger equation solver is discussed with a particular focus on electronic structure simulations that normally involve sparse system matrices of 107 or larger degrees of freedom. The solver shows remarkable performance enhancement with Intel Xeon Phi coprocessors indicating the capability of large-scale simulations with less computing nodes compared to the case when multi-core processors are only used. Details of parallelization scheme, numerical solver, and strategy for performance improvement with many-core processors are presented to establish a sound framework of electronic structure simulations with many-core computing. Hoon Ryu, Yosang Jeong	CLUSTER	1