Precise reagent mixing in user-defined ratios is a fundamental requirement in many microfluidic applications, including diagnostics, chemical synthesis, and biological assays. However, existing solutions for ratio-specific mixing often rely on complex active components, such as multiple pressure sources, flow controllers, or on-chip valves, making them costly, bulky, and unsuitable for portable or low-resource settings. In this work, we present a mixer design and a synthesis method for generating 3D-printable microfluidic devices that achieve ratiospecific mixing using only a single constant pressure source. Our method decomposes the desired mixing ratio into additive subcomponents, each represented by a dedicated inlet channel with a tailored length to enforce the correct hydraulic resistance. The method outputs a complete microfluidic layout, ready for direct fabrication via 3D printers. We validate our approach through numerical simulations and physical prototyping across eight diverse mixing scenarios. Results show that the achieved mixing ratios closely resemble the target, demonstrating the method’s accuracy and robustness. This work enables low-cost, portable, and accessible microfluidic devices for ratio-specific solution delivery, broadening the scope of microfluidics in settings where simplicity, reproducibility, and affordability are critical.

The sustained growth of high-performance computing (HPC) workloads places increasing pressure on on-chip communication, where data movement, bandwidth, and power budget have become primary limiting factors. Optical networks-on-chip (ONoCs), particularly wavelength-routed ONoCs (WRONoCs), offer a transformative path toward ultra-high-speed and energy-efficient communication. The design of a WRONoC involves a complex interplay between two main design aspects: logic connection design (topological design) and layout synthesis (physical design). Existing design methodologies either separate the two design aspects into two sequential steps, which is computationally affordable but prone to suboptimality, or perform concurrent optimization that is theoretically holistic but computationally intractable. Such inefficiencies limit the scalability and generalizability of WRONoCs. To address these challenges, this paper presents two advanced design methodologies that have demonstrated their effectiveness in synthesizing high-performance WRONoCs. By pre-integrating layout constraints into the topological design phase, the logic connections created by both methodologies can be compatible with physical design, thereby resolving the long-standing conflict between solution quality and synthesis overhead.

Multilayered continuous-flow microfluidic biochips are rapidly advancing platforms for delicate bio-applications. The high complexity of biochip structures and application protocols drives the growing demand for design automation solutions. Current research enables the automatic synthesis of the physical layout and the scheduling and binding protocols of biochips, showcasing the significant potential of microfluidic design automation for improved resource utilization and reduced bioassay completion time. However, state-of-the-art synthesis methods primarily focus on device and operation levels, assuming flow paths are always available and neglecting interactions of flow and control channels. This creates a critical gap in the synthesis process, causing performance degradation, resource redundancy, or even infeasible designs. This work bridges this gap with a two-stage approach. Firstly, we perform a mathematical model to synthesize a high-level protocol that specifies the paths and execution orders of fluid transportation operations. Specifically, we construct flow paths based on the fluidic architecture of a given biochip design and optimize scheduling schemes to minimize the completion time of a given bioassay. Next, we perform a simulation-based synthesis of control channel pressurization sequences to realize the high-level protocol. Experimental results confirm that the proposed approach efficiently validates flow paths for feasible designs, identifies conflicting design features in infeasible designs, and improves the design efficiency and quality: compared to the original designs, it reduces the average number of control channels by 49%, and compared to the preliminary work, it reduces the average fluid transportation time by 19% and the average program run time by 38%.

Inkjet-printed electronics is a low-cost option for large-scale production. To avoid manufacturing defects, recent research has considered design constraints, such as Laplace and proximity conflicts, decomposed the layouts into different layers, and printed them sequentially. The state-of-the-art work reduced the manufacturing time by optimizing the number of layers and drying time. In this work, we aim to enhance manufacturing efficiency from a new angle, concurrently optimizing the printing time and the layout decomposition of inkjet-printed electronics. We propose an integer linear programming formulation and a dynamic programming algorithm to determine layout decomposition and layer assignment and to estimate the total printing time by carefully considering printing characteristics and design constraints. Experimental results demonstrate significant reductions in overall printing time, leading to improved fabrication efficiency.

Multilayered continuous-flow microfluidic biochips are highly valued for their miniaturization and high bio-application throughput. However, challenges arise as the dynamic connections of channels, adjusted to satisfy varying demands of fluid transportation at different moments, complicate the execution of bioassays. The existing methods often focus on device binding and operation scheduling during high-level synthesis but overlook the topological connections within the microfluidic network. This oversight leads to mismanagement of conflicts between fluid transportations and erroneous assumptions about constant flow velocities, resulting in decreased accuracy and efficiency or even infeasibility of bioassay execution. To address this problem, we mathematically model the flow velocity that varies according to the dynamic changes of the topological connections between the on-chip components during the execution of the bioassay. Further integrating the flow velocity model into the high-level synthesis, we propose a quadratic programming (QP) method that constructs flow paths and optimizes scheduling schemes to minimize the bioassay completion time. Experimental results confirm that, compared with the state-of-the-art approach, our method shortened the bioassay completion time by an average of 40.9%.

Optical networks-on-chips (ONoCs), which adopt optical waveguides, microring resonators (MRRs), and the wavelength division multiplexing (WDM) scheme to transmit optical signals, serve as promising solutions for integrating multi- and many-core systems to provide high-bandwidth, low-latency, and low-power on-chip communication. To minimize the insertion loss of a wavelength-routed ONoC (WRONoC) during physical implementation, existing studies either adopt conventional standard cell placement techniques or maximally avoid waveguide crossings; however, all of them ignore the fact that the critical path suffering from the maximum insertion loss dominates the overall power efficiency and system performance. In this work, we propose CPONoC, a critical-path-aware physical implementation tool for WRONoCs. Different from existing studies, CPONoC focuses on minimizing the insertion loss of the critical path using an iterative crossing-aware force-directed method, and it is compatible with different representative logic schemes and input configurations. Compared to the state-of-the-art design automation tools, CPONoC achieves an average reduction of 9.6% in maximum insertion loss.

3D printing has revolutionized microfluidic device fabrication, enabling rapid prototyping and intricate geometries. However, designing lab-on-a-chip systems remains challenging. In microfluidic devices, precise control over fluid behavior is crucial, requiring careful attention to both timing and volume. Current state-of-the-art design automation tools for microfluidics have limitations, particularly in addressing the specific challenges of 3D-printed microfluidics and user-defined timing and volumetric constraints, and no design synthesis tool exists targeting these domains. We present 3M-DeSyn, a novel design synthesis method for 3D-printed microfluidics that incorporates timing and volumetric constraints and outputs print-ready 3D modeling files. It automates the design process, allowing users to specify schematics and desired flow control parameters. The underlying methodology is based on mathematical modeling of fluidic behavior and utilizes constraint optimization programming to find optimized solutions. Experimental results show significant improvements in design time while enabling rapid development of custom microfluidic systems.

Wavelength-routed networks-on-chip (WRONoCs) are known for providing high-speed and low-power communication. Despite those advantages, the key components, microring resonators (MRRs), are prone to process and thermal variations, which cause signals to fail to reach their intended destinations. Thus, several WRONoC fault-tolerant methods propose to prepare a constant number of backups, which often leads to inefficient resource allocation, i.e. insufficient backups for the signals that are prone to errors, while more than enough backups for the signals that are barely affected, resulting in much power waste. In this work, we propose a dynamical backup resource allocation method for reliability maximization and power minimization in WRONoCs. Precisely, our method starts with accurately modeling the WRONoC faults, which considers the deviation of an MRR's default behavior as a Gaussian Distribution. Since signal paths consist of different numbers of MRRs, and the signals have different probabilities of deviating from their designated paths, our method customizes the number of backup paths for every signal and automatically allocates the minimum resources to optimize the reliability.

With low latency and collision-free communication, wavelength-routed optical networks-on-chip (WRONoC) become an effective solution to the growing demands for multi-core communications. Microring resonators (MRRs), the primary optical components in WRONoC, are susceptible to process variation. Under process variation, the MRR’s transmission spectrum shifts, results reduced signal power and increased crosstalk. However, the impacts caused by process variation have not yet been considered in WRONoC designs. In this work, we propose a methodology to optimize the MRR radii and signal wavelengths to counter process variation. Specifically, we construct analytical models of expected signal power under MRR process variation and develop optimization methods to maximize the expected signal transmission power in WRONoC. Results show up to 7.51 dB improvement in worst-case expected signal transmission power compared to designs that do not consider process variation.

Continuous-flow microfluidic chips are multilayered miniaturized platforms to manipulate small volumes of fluids with valves. There are two types of channels on a chip: flow channels for the reaction of fluids, and control channels for the actuation of valves. Multiplexers (MUXes) are essential microfluidic components for individually addressing many flow channels with few control channels. As the integration scale of microfluidic chips increases, the reliability of MUXes becomes a critical concern, as a single defective control channel in a MUX will affect a large part of the flow channels addressed by the MUX. This paper formally analyzes and identifies the design rules for a MUX to tolerate n defective control channels, and model the fault-tolerant MUX (FT-MUX) design problem as a binary constant weight code problem to minimize resource overheads. We demonstrate that FT-MUX improves resource efficiency by up to hundreds of times compared to the conventional fault-tolerant design method. Besides, given no less than 10 control channels, FT-MUX tolerates at least one defective control channel and addresses even more flow channels with equal or fewer resources than a standard MUX. The advantages become more significant as the integration scale increases.

As an emerging platform for biochemical experiments, flow-based microfluidic biochips are currently suffering from malfunctions caused by manufacturing defects, thereby having low yield. While many related studies have been conducted and reliability quantification models have been published, layout optimization methods are yet lacking. In this paper, we propose AutoRE, the first tool to automatically enhance reliability by optimizing layouts. AutoRE varies the layout within a certain range without changing its topology, and adopts Bayesian optimization (BO) to identify the most reliable variant. Experimental results demonstrate that AutoRE can efficiently and effectively improve the reliability across all testcases by around 40% on average.

Sample preparation, where a certain number of reagents must be mixed in a specific volumetric ratio, is an integral step for various bio-assays. A programmable microfluidic device (PMD) is an advanced flow-based microfluidic biochip (FMB) platform, that considered to be very effective for sample preparation. However, the impact of mixer placement, reagents' distribution, and mixing time on the automation of sample preparation has not yet been investigated. We consider a mixing efficiency model controlled by the number of alternations “μ” of reagents along the mixing circulation path and propose a loading-aware placement strategy that maximizes the mixing efficiency. We use satisfiability modulo theories (SMT) and propose a one-pass strategy for placing the mixers and the reagents, that successfully enhance the loading and mixing efficiencies.

Wavelength-routed optical networks-on-chip (WR-ONoCs) attract ever-increasing attention for supporting high-speed communications with low power and latency. Among all WRONoC routers, optical ring routers attract much interest for their simple structures. However, current designs of ring routers have overlooked the customization problem: when adapting to applications that have specific communication requirements, current designs suffer high propagation loss caused by long worst-case signal paths and high splitter usage in power distribution networks (PDN). To address those problems, we propose a novel customization method to generate application-specific ring routers with multiple sub-rings, SRing. Instead of sequentially connecting all nodes in a large ring, we cluster the nodes and connect them with sub-ring waveguides to reduce the path length. Besides, we propose a mixed integer linear programming model for wavelength assignment to reduce the number of PDN splitters. We compare SRing to three state-of-the-art ring router design methods for six applications. Experimental results show that SRing can greatly reduce the length of the longest signal path, the worst-case insertion loss, and the number of splitters in the PDN, significantly improving the power efficiency.

To meet the increasing demand for high-speed communication in many-cores systems, optical networks-on-chip (ONoCs) have gained attention for their ability to deliver low-latency and high-bandwidth data transmission. As a specific type of ONoCs, wavelength-routed ONoCs (WRONoCs) offer exclusive benefits such as collision-free and arbitration-free communication between cores. To guide the design and optimization of WRONoCs, many simulators have been developed to model WRONoC behavior at the device and circuit levels, offering detailed insights into photonic components. These tools have significantly advanced photonic design. As WRONoCs move closer to practical applications, network-level simulation becomes increasingly important for evaluating end-to-end communication behavior. Despite the need, existing simulators rarely support WRONoC modeling at the network level, leaving a critical gap in current toolchains. To address that, we propose the first network-level WRONoC simulation platform, WROXIM, adapted from an open-source NoC simulator, Noxim. It supports cycle-accurate modeling of optical communication behaviors and retains full compatibility with traditional electrical NoC simulations. To model realistic communication behaviors, WROXIM incorporates both optical and electrical components, including serializers, deserializers, waveguides, buffers, and processing elements (PEs). This modeling approach allows the simulator to capture end-to-end data movement from a PE through the optical interconnect to another PE. Given an application with multiple tasks, WROXIM supports task-driven workloads and provides key performance metrics such as latency, throughput, and energy consumption, offering a platform for design exploration and verification for WRONoCs.

The "CAD Contest at ICCAD" is a challenging, multi-month, research and development competition, focusing on advanced, real-world problems in the field of electronic design automation (EDA). Since 2012, the contest has been publishing many sophisticated circuit design problems, from system-level design to physical design, together with industrial benchmarks and solution evaluators. Contestants can participate in one or more problems provided by EDA/IC industry. The winners will be awarded at an ICCAD special session dedicated to this contest. Every year, the contest attracts more than a hundred teams, fosters productive industry-academia collaborations, and leads to hundreds of publications in top-tier conferences and journals. The 2025 CAD Contest has 247 teams from all over the world, which generates the highest participation record. Moreover, the problems of this year cover state-of-the-art EDA research trends such as hardware trojan detection, design optimization with multibit flip-flops, and performance-driven incremental placement optimization from well-known EDA/IC companies. We believe the contest keeps enhancing impact and boosting EDA researches.

Wavelength-routed optical networks-on-chip (WRONoC) is a promising solution for achieving high-bandwidth, low-power on-chip communications. Previous work has aimed to reduce transmission latency in WRONoC by bandwidth allocation considering application communication demands. This is achieved by optimizing core-to-port mapping and configuring the radii of microring resonators (MRRs), which are the key routing components in WRONoC. However, previous work suffers from slow runtime and limited solution quality and fails to obtain feasible solutions for large applications given WRONoC topology. To address these, we propose a novel graph-based approach, FAB, to fast and efficiently reduce transmission latency in WRONoC. Specifically, we formulate core-to-port mapping and MRR radii configuration as two-stage weighted subgraph matching problems. In each stage, we construct graphs to model the demands or the bandwidth potential between vertices. By introducing strict weight-based matching strategies and progressively relaxing infeasible cases, FAB can quickly achieve optimized high-quality solutions. Experimental results demonstrate that FAB reduces worst-case transmission latency by up to 87.5% and accelerates optimization by up to 500,000× compared to the state-of-the-art method.

Inkjet-printed electronics has attracted considerable attention for low-cost mass production. High-density inkjet-printed designs can benefit from printing and drying in batches to avoid defects due to undesired ink redistribution and ink merging. The state-of-the-art approach decomposes the design into small objects, assigns the objects to different layers to be printed in different iterations, and minimizes the number of layers to reduce the number of iterations. However, it overlooks the differences in the printing and drying time between different layers and thus cannot properly model the impact of different layer assignment solutions on the manufacturing cycle time. In this work, we propose a row-based printing model that simulates the inkjet-printing mechanism and an integral Gaussian drying model that evaluates the local evaporation rate to approximate the printing and drying process of inkjet-printed manufacturing. Based on these models, we propose a mixed-integer-linear programming (MILP) method called the manufacturing model to minimize the manufacturing cycle time and avoid defects by optimally assigning objects to different iterations to be printed and dried in batches. Experimental results confirm that, compared with the preliminary work, manufacturing using our optimized solutions required up to 42.7% less time.

Flow-based microfluidic biochips have emerged as a promising platform for biochemical experiments. These chips contain transportation channels and operational devices that are controlled by microvalves, which are actuated by external controllers. As the complexity of experiments conducted on these chips continues to increase, control multiplexers (MUXes) have become essential for actuating a large number of valves. However, current binary-coding-based MUXes do not fully utilize the coding capacity and suffer from reliability issues due to long total length of channels and high control channel density. In this article, we propose the combinatorial coding, a novel MUX coding strategy, along with an algorithm to synthesize combinatorial-coding-based MUXes (CoMUXes) of arbitrary sizes with the theoretical maximum coding capacity. We also develop a simplification method to reduce the number of valves and the total length of control channels in CoMUXes, thereby improving their reliability. Additionally, we develop a reliability-aware adaptation method to reliably integrate the CoMUXes into the main functional part of the designs. We compare CoMUX with state-of-the-art MUXes under different control demands with up to$10 \times 2^{13}$independent control channels. Experimental results show that CoMUXes can reliably address more independent control channels with fewer resources. For instance, when the number of control channels to be controlled is up to$10 \times 2^{13}$, compared to a state-of-the-art MUX, the optimized CoMUX reduces the number of required flow channels by 44% and the number of valves by 90%. The proposed adaptation method is also tested to be capable of significantly reducing area usage, total length of control channels, and the risk of having defects.

Control channels on microfluidic large-scale integration (mLSI) chips are prone to blockage and leakage defects. In this work, we propose a built-in self-test (BIST) method that drastically improves the test efficiency. Given n to-be-tested control channels, we reduced the number of test patterns for blockage and leakage tests from [EQUATION] to 1, and from ⌈log2(n + 1)⌉ to ⌈log2(χ(G) + 1)⌉, respectively, where χ(G) denotes the vertex chromatic number of a graph G consisting of n vertices. We fabricated our design and demonstrated the feasibility and efficiency of our method.

After decades of development, flow-based microfluidic biochips have become an increasingly attractive platform for biochemical experiments. The fluid transportation and the on-chip device operation are controlled by microvalves, which are driven by external pneumatic controllers. To meet the increasingly complex experimental demands, the number of microvalves has significantly increased, making it necessary to adopt multiplexers (MUXes) for the actuation of microvalves. However, existing MUX designs have limited coding capacities, resulting in area overhead and excessive chip-to-world interface. This paper proposes a novel gate structure for modifying the current MUX architecture, along with a mixed coding strategy that achieves the maximum coding capacity within the modified MUX architecture. Additionally, an efficient synthesis tool for the mixed-coding-based MUXes (LaMUXes) is presented. Experimental results demonstrate that the LaMUX is exceptionally efficient, substantially reducing the usage of pneumatic controllers and microvalves compared to existing MUX designs.

Wavelength-routed optical networks-on-chip (WRONoCs) are well-known for providing high-speed and collision-free communication in multi-core processors. Previous work was unable to simultaneously reduce the design complexity and total optical power consumption of WRONoC. Besides, in current designs, each microring resonator (MRR), which is the key component of WRONoC, is configured to demultiplex to one specific wavelength. This significantly increases the MRR usage and the insertion loss. In this work, we adapt different types of ONoC routers into the mesh-based template. To reduce MRR usage, we take advantage of an important feature of MRR, multi-resonance, so that a single MRR can demultiplex signals on multiple wavelengths. To this end, we propose an efficient design method that synthesizes mesh-based WRONoCs using multi-resonance MRRs and existing optical routers to reduce total power consumption. The experimental results show that our method outperforms state-of-the-art design methods in significantly reducing MRR usage and optical power.

With the rapid development of integrated photonic technology, wavelength-routed optical networks-on-chip (WRONoC) is emerging as a high-potential computing architecture due to its low power consumption, high bandwidth, and conflict-free communication advantages. Previous works utilize the multi-resonance properties of the microring resonator (MRR), the key component in WRONoC, to transmit multiple signals on different wavelengths in one transmission path, thereby achieving parallel communication. However, they do not consider the demands of the actual application communication bandwidth. If communications with high bandwidth demands are not allocated with highly parallel transmission paths, they may become the bottleneck of the network, resulting in increased transmission cycles and overall data transmission time. In this work, we propose an optimization strategy that allocates signal wavelengths for each communication based on its actual bandwidth demand to reduce communication time. Specifically, based on the actual bandwidth demands and topology structure, we first map the communication nodes in the target application to the ports of a WRONoC topology. Next, we optimize the radii of MRRs in the topology and allocate the signal wavelengths to each transmission path to minimize the worst-case data transmission cycle. Experimental results show that, compared to methods that only consider communication parallelism, our strategy can reduce the worst-case of data transmission cycles by over five times, thereby significantly decreasing the time required for data transmission.

The "CAD Contest at ICCAD" is a challenging, multi-month, research and development competition, focusing on advanced, real-world problems in the field of electronic design automation (EDA). Since 2012, the contest has been publishing many sophisticated circuit design problems, from system-level design to physical design, together with industrial benchmarks and solution evaluators. Contestants can participate in one or more problems provided by EDA/IC industry. The winners will be awarded at an ICCAD special session dedicated to this contest. Every year, the contest attracts more than a hundred teams, fosters productive industry-academia collaborations, and leads to hundreds of publications in top-tier conferences and journals. The 2024 CAD Contest has 221 teams from all over the world, which generates the highest participation record. Moreover, the problems of this year cover state-of-the-art EDA research trends such as logic optimization, multibit flip-flop, and Machine Learning (ML) for EDA from well-known EDA/IC companies. We believe the contest keeps enhancing impact and boosting EDA researches.

After decades of development, flow-based microfluidic biochips have become one of the most promising platforms for biochemical experiments. Control ports, which are remarkably area-consuming punch holes, are interfaces to external pneumatic controllers. To prevent the inserted outer catheters from hindering microscopic observation during experiments, control ports are placed on chip boundaries in practice. In this paper, we propose a practical and novel control layer escape routing methodology, which efficiently connects microvalves to user-specified boundaries. Particularly, the proposed methodology groups certain microvalves, and constructs a tree to connect them with the same control port, which is regarded as the root of the tree. Clustering more microvalves into the same group can reduce the usage of control ports, but will lead to more intensive connections among microvalves, which becomes larger obstacles for the routing of other microvalves outside the group, thereby reducing the routability. To derive an optimized tradeoff between the control port usage and the routability, we adapt a hierarchical clustering algorithm with a dynamically changing threshold that ascertains the closeness of the microvalves. We also adopt the Bayesian optimization (BO) to determine the optimized routing order for better routing results. Additionally, we propose a fault-tolerant structure as an option for users, which only occupies little area around control channels, and significantly improves the reliability against blockage defects. Experimental results demonstrate that the proposed methodology can efficiently connect all microvalves to user-specified boundaries, significantly reduce control port usage, shorten control channels, and improve reliability compared to baseline methods.

Wavelength-routed optical networks-on-chip (WR-ONoCs) are well-known for supporting high-bandwidth communications with low power and latency. Among all WRONoC routers, optical ring routers have attracted great research interest thanks to their simple structure, which looks like concentric cycles formed by waveguides. Current ring routers are designed manually. When the number of network nodes increases or the position of network nodes changes, it can be difficult to manually determine the optimal design options. Besides, current ring routers face two problems. First, some signal paths in the routers can be very long and suffer high insertion loss; second, to connect the network nodes to off-chip lasers, waveguides in the power distribution network (PDN) have to intersect with the ring waveguides, which causes additional insertion loss and crosstalk noise. In this work, we propose XRing, which is the first design automation method to automatically synthesize optical ring routers based on the number and position of network nodes. In particular, XRing optimizes the waveguide connections between the network nodes with a mathematical modelling method. To reduce insertion loss and crosstalk noise, XRing constructs efficient shortcuts between the network nodes that suffer long signal paths and creates openings on ring waveguides so that the PDN can easily access the network nodes without causing waveguide crossings. The experimental results show that XRing outperforms other WRONoC routers in reducing insertion loss and crosstalk noise. In particular, more than 98% of signals in XRing do not suffer first-order crosstalk noise, which significantly enhances the signal quality.

After decades of development, flow-based microfluidic biochips have become a revolutionary platform for biochemical experiments. To meet the increasingly complex experimental demands, the length and density of channels in these chips grow significantly, which brings about higher defect probabilities. Till now, several methods have been proposed to improve the yield of these increasingly complex chips. However, the effectiveness of these methods cannot be properly evaluated, since there has been no method that systematically analyzes the reliability of a microfluidic design. In this paper, we propose the first mathematical models to quantify the reliability of a microfluidic design by calculating the probability of blockage and leakage defects happening to the design. Besides, we propose a graph-transformer-based method to speed up the calculation, so that designers can have a fast and accurate evaluation of the reliability of a microfluidic design at any scale.

In high-performance printed circuit boards (PCBs), adding serpentine delay lines is the most prevalent delay-matching technique to balance the delays of time-critical signals. Serpentine topology, however, can induce simultaneous accumulation of the crosstalk noise, resulting in erroneous logic gate triggering and speed-up effects. The state-of-the-art approach for crosstalk alleviation achieves waveform integrity by enlarging wire separation, resulting in an increased routing area. We introduce a method that adopts spiral delay lines for delay matching to mitigate the speed-up effect by spreading the crosstalk noise uniformly in time. Our method avoids possible routing congestion while achieving a high density of transmission lines. We implement our method by constructing a mixed-integer-linear programming (MILP) model for routing and a quadratic programming (QP) model for spiral synthesis. Experimental results demonstrate that our method requires, on average, 31% less routing area than the original design. In particular, compared to the state-of-the-art approach, our method can reduce the magnitude of the crosstalk noise by at least 69%.

Microfluidic large-scale integration (mLSI) is a promising lab-on-a-chip platform for high-throughput bio-applications. Due to the high integration scale and the small feature size, control channels on mLSI chips are prone to blockage and leakage defects, which may lead to faulty behavior of valves and erroneous experimental results. Thus, mLSI chips need to be tested before usage. Current mLSI-tests are mostly performed in a straightforward way by testing each valve individually, which is very time consuming and error prone. As the integration scale of mLSI chips keeps increasing, there is a pressing demand for more efficient test approaches. This work proposes the first built-in-self-test (BIST) method for mLSI with an integrated test module design. Instead of testing individual valves, the proposed method directly tests the control channels and thus greatly improves the test efficiency. Only${}({n}/{2})$and$\lceil \log _{2}(n+1)\rceil $test operations are required to test the blockage and leakage defects, respectively, of$n$control channels. The proposed test module consumes moderate area overhead and the test method is easy to operate. Neither specialized software nor external pressure sensors are required for carrying out the tests. Experiments show that our test approach is sensitive enough to detect defects that have a feature size as small as 10$\mu \text{m}$and that are several centimeters away from the test module.

Microfluidic large-scale integration (mLSI) biochips have developed rapidly in recent decades. The gap between design efficiency and application complexity has led to a growing interest in mLSI design automation. The state-of-the-art design automation tools for mLSI focus on the simultaneous co-optimisation of the flow and control layers but neglect potential contamination between different fluid reagents and products. Microfluidic switches, as fluid routers at the intersection of flow paths, are especially prone to contamination. State-of-the-art tools design the switches as spines with junctions, which aggregate the contamination problem. In this work, we present a contamination-free microfluidic switch design and a synthesis method to generate application-specific switches that can be employed by physical design tools for mLSI. We also propose a scheduling and binding method to transport the fluids with least time and fewest resources. To reduce the number of pressure inlets, we consider pressure sharing between valves within the switch. Experimental results demonstrate that our methods show advantages in avoiding contamination and improving transportation efficiency over conventional methods.

Flow-based microfluidic chips are one of the most promising platforms for biochemical experiments. Transportation channels and operation devices inside these chips are controlled by microvalves, which are driven by external pressure sources. As the complexity of experiments on these chips keeps increasing, control multiplexers (MUXes) become necessary for the actuation of the enormous number of valves. However, current binary-coding-based MUXes do not take full advantage of the coding capacity and suffer from the reliability problem caused by the high control channel density. In this work, we propose a novel MUX coding strategy, named Combinatorial Coding, along with an algorithm to synthesize combinatorial-coding-based MUXes (CoMUXes) of arbitrary sizes with the proven maximum coding capacity. Moreover, we develop a simplification method to reduce the number of valves and control channels in CoMUXes and thus improve their reliability. We compare CoMUX with the state-of-the-art MUXes under different control demands with up to 10 × 213 independent control channels. Experiments show that CoMUXes can reliably control more independent control channels with fewer resources. For example, when the number of the to-be-controlled control channels is up to 10 × 213, compared to a state-of-the-art MUX, the optimized CoMUX reduces the number of required flow channels by 44% and the number of valves by 90%.

Optical network-on-chip (ONoC) is an emerging upgrade for electronic network-on-chip (ENoC). As a kind of ONoC, wavelength-routed ONoC (WRONoC) shows ultrahigh bandwidth and ultralow latency in data communication. Manually designed WRONoC topologies typically reserve all to all links. This causes the waste of resources. Topology customization for each individual communication network can save resources, but requires automation for efficient design. The state-of-the-art design automation method is not efficient and does not support crosstalk analysis and signal-to-noise ratio (SNR) optimization. Moreover, the state of the art does not consider the physical locations of the data sending/receiving ports, causing unavoidable detours and crossings in the physical layout. In this work, we present FAST+: an automatic topology customization and optimization method. Compared with the state of the art, FAST+ operates much more efficiently and proposes a concrete router-level crosstalk-analysis method and a novel SNR optimization algorithm. This work also provides solutions to avoid detours and crossings in the physical layout. When SNR optimization is not enabled, experimental results show that FAST+ runs thousands times faster than the state of the art on average while providing multiple better or equally good topologies regarding resource usage and the worst case insertion loss. When SNR optimization is enabled, FAST+ provides$1.75\times $better worst case SNR on average after the optimization while not sacrificing resource usage and the worst case insertion loss.

Wavelength-routed optical networks-on-chip (WRONoCs) are known for delivering collision- and arbitration-free on-chip communication in many-cores systems. While appealing for low latency and high predictability, WRONoCs are challenged by scalability concerns due to two reasons: (1) State-of-the-art WRONoC topologies use a large number of microring resonators (MRRs) which result in much MRR tuning power and crosstalk noise. (2) The positions of master and slave nodes in current topologies do not match realistic layout constraints. Thus, many additional waveguide crossings will be introduced during physical implementation, which degrades the network performance. In this work, we propose an N x (N - 1) WRONoC topology: Light with a 4 x 3 router Hash as the basic building block, and a simple but efficient approach to configure the resonant wavelength for each MRR. Experimental results show that Light outperforms state-of-the-art topologies in terms of enhancing signal-to-noise ratio (SNR) and reducing insertion loss, especially for large-scale networks. Furthermore, Light can be easily implemented onto a physical plane without causing external waveguide crossings.

Optical network-on-chip (ONoC) is an emerging upgrade for electronic network-on-chip (ENoC). As a kind of ONoC, wavelength-routed optical network-on-chip (WRONoC) shows ultra-high bandwidth and ultra-low latency in data communication. Manually designed WRONoC topologies typically reserve all to all communications. Topologies customized for application-specific networks can save resources, but require automation for their efficient design. The state-of-the-art design automation method proposes an integer-linear-programming (ILP) model. The runtime for solving the ILP model increases exponentially with the growth of communication density. Besides, the locations of the physical ports are not taken into consideration in the model. This causes unavoidable detours and crossings in physical layout. In this work, we present FAST: an automatic topology customization and optimization method combining ILP and a sweeping technique. FAST overcomes the runtime problem and provides multiple topology variations with different port orders for physical layout. Experimental results show that FAST is thousands times faster when tackling dense communications and ten to thousands times faster when tackling sparse communications while providing multiple better or equivalent topologies regarding resource usage and the worst-case insertion loss.

Inkjet-printed electronics have attracted considerable attention for low-cost mass production. To avoid undesired device behavior due to accidental ink merging and redistribution, high-density designs can benefit from layering and drying in batches. The overall manufacturing cycle-time, however, now becomes dominated by the cumulative drying time of these individual layers. The state-of-the-art approach decomposes the whole design, arranges the modified objects in different layers, and minimizes the number of layers. Fewer layers imply a reduction in the number of printing iterations and thus a higher manufacturing efficiency. Nevertheless, printing objects with significantly different drying dynamics in the same layer leads to a reduction of manufacturing efficiency, since the longest drying object in a given layer dominates the time required for this layer to dry. Consequently, an accurate estimation of the individual layers' drying time is indispensable to minimize the manufacturing cycle-time. To this end, we propose the first Gaussian drying model to evaluate the local evaporation rate in the drying process. Specifically, we estimate the drying time depending on the number, area, and distribution of the objects in a given layer. Finally, we minimize the total drying time by assigning to-be-printed objects to different layers with mixed-integer-linear programming (MILP) methods. Experimental results demonstrate that our Gaussian drying model closely approximates the actual drying process. In particular, comparing the non-optimized fabrication to the optimized results demonstrates that our method is able to reduce the drying time by 39%.

To meet the ever-increasing requirements of on-chip communication, the trend is towards wavelength-routed optical networks-on-chip (WRONoCs), which support high-speed communication with low power. A typical WRONoC design flow consists of two consecutive steps: topological design and physical design. Current physical design tools interpret the input topology as a pure logic scheme and perform placement and routing for all network components from scratch. Due to the large design complexity and the layout constraints, additional waveguide crossings in the synthesized layouts are hardly avoidable, which results in an increase in insertion loss and crosstalk noise and thus degrades the network performance. In this work, we propose a physical design tool, ToPro, which retains the interconnection among the optical switching elements by projecting the structure of a WRONoC topology onto the physical plane, and focuses on the waveguide routing to the IP-cores. To avoid the increase in insertion loss and crosstalk noise, ToPro removes the extra crossings and long detours of waveguides by changing the routing order of nets. The experimental results demonstrate the superiority of ToPro in time- and energy-efficiency. For example, compared to a state-of-the-art design automation tool, ToPro synthesizes a network with 16 IP-cores with a 17% reduction on the worst-case insertion loss and decreases the synthesis time from more than six days to less than one second.

The rapid development of microfluidic biochips requires matching automated synthesis methods. In particular, high-level synthesis methods for microfluidic chips need to consider various bio-constraints regarding time and device occupancy. Recent biochemical applications show that the duration of some bio-operations cannot be predicted in advance, which increases the likelihood that current synthesis methods would waste on-chip resources or even violate given bio-constraints. In this work, we present a relative-scheduling-based high-level synthesis method to optimize the bio-assay schedules and the usage of on-chip devices considering bio-operations with indeterminate durations. Experimental results show that our method significantly reduces the total execution time of bioassays without violating bio-constraints when using the same on-chip resources.

Enabled by recent development in silicon photonics, wavelength-routed optical networks-on-chips (WRONoCs) emerge as an appealing next-generation architecture for the communication in multiprocessor system-on-chip. WRONoCs apply a passive routing mechanism that statically reserves all data transmission paths at design time, and are thus able to avoid the latency and energy overhead for arbitration, compared to other ONoC architectures. Current research mostly assumes that in a WRONoC topology, each initiator node sends one bit at a time to a target node. However, the communication parallelism can be increased by assigning multiple wavelengths to each path, which requires a systematic analysis of the physical parameters of the silicon microring resonators and the wavelength usage among different paths. This work proposes a mathematical modeling method to maximize the communication parallelism of a given WRONoC topology, which provides a foundation for exploiting the bandwidth potential of WRONoCs. Experimental results show that the proposed method significantly outperforms the state-of-the-art approach, and is especially suitable for application-specific WRONoC topologies.

Optical Networks-on-Chip (ONoCs) are becoming increasingly attractive for intra-chip communications due to their low power-perbit requirements and high bandwidth. Wavelength-Routed ONoCs (WRONoCs), a subtype of ONoCs, further reduce network latency. Recently, tools to design WRONoCs have been developed, but these tools are still incomplete as they do not yet consider key design aspects such as the type of laser source used and the impact of the laser Power Distribution Network (PDN) on the laser power consumption. In this work we propose the first design automation tool to combine awareness of both on-chip and off-chip lasers with optimization of both the logical topology and the physical layout of WRONoCs for application-specific designs. Compared to previous works, the incorporation of the type of laser and the PDN into the optimization process combined with a new Generic Routing Unit (GRU) placement method leads to a laser power reduction of up to 20%.

Optical networks-on-chip (ONoCs) are a promising solution for high-performance multicore integration with better latency and bandwidth than traditional electrical NoCs. Wavelength-routed ONoCs (WRONoCs) offer yet additional performance guarantees. However, WRONoC design presents new EDA challenges which have not yet been fully addressed. So far, most topology analysis is abstract, i.e., overlooks layout concerns, while for layout the tools available perform place and route (P&R) but no topology optimization. Thus, a need arises for a novel optimization method combining both aspects of WRONoC design. In this article, such a method, PSION+, is laid out. This new procedure uses a linear programming model to optimize a WRONoC physical layout template to optimality. This template-based optimization scheme is a new idea in this area that seeks to minimize problem complexity while keeping design flexibility. A simple layout template format is introduced and explored. Finally, multiple model reduction techniques to reduce solver run-time are also presented and tested. When compared to the state-of-the-art design procedure, results show a decrease in maximum optical insertion loss of 41%.

Multilayered valve-based continuous-flow microfluidic biochips are a rapidly developing platform for delicate bio-applications. Due to the high complexity of the biochip structure and the application protocols, there is an increasing demand for design automation approaches. Current research has enabled automated generation of biochip physical designs, operation scheduling, and binding protocols, which has demonstrated the potential for better resource utilization and execution time reduction. However, the state-of-the-art high-level synthesis methods are on operation- and device-level. They assume fluid transportation paths to be always available but overlook the physical layout of the control and flow channels. This mismatch leads to a gap in the complete synthesis flow, and can result in performance drop, waste of resources due to redundancy or even infeasible designs. This work proposes to bridge this gap with a simulation-based approach, which takes a biochip design and a high-level protocol as inputs, and synthesizes channel-level pressurization protocols to support dynamic construction of valid fluid transportation paths. Experimental results show that the proposed method can efficiently validate and optimize the flow paths for feasible designs and protocols, detect redundant resource usage, and locate the conflicts for infeasible designs and protocols. It opens up a new direction to improve the performance and the feasibility of customized biochip synthesis.

Design automation for continuous-flow microfluidic large-scale integration (mLSI) biochips has made remarkable progress over the past few years. Nowadays a biochip containing up to hundreds of components can be automatically synthesized within a few minutes. However, the current advanced design automation tools are mostly developed for research use, which focus essentially on the algorithmic performance but overlook the accessibility. Therefore, we have started the Cloud Columba project since 2017 to provide users from different backgrounds with easy access to the state-of-the-art design automation approaches. Without being limited by the computing power of their end devices, users just need to formulate their design requests in a high abstraction level, based on which the cloud server will automatically synthesize a customized manufacturing-ready biochip design, which can be viewed and stored using simply a web browser. With the computer-synthesized designs, Cloud Columba supports application developers to explore a wider range of possibilities, and algorithm developers to validate and improve their ideas based on a practical foundation.

Wavelength-routed optical network-on-chip (WRONoC) design consists of topological and physical synthesis. It covers many interacting design aspects such as wavelength assignment, message routing, network construction, component placement, and waveguide routing. Due to the high complexity of the design problem, current manual design usually trades optimality for scalability and feasibility, which results in performance degradation and waste of resources. In this paper, we will present an overview of the existing design automation approaches that have demonstrated their effectiveness in customizing and optimizing application-specific WRONoC designs, and of the potential design automation directions to address a wider range of design challenges. We will also discuss the advantages of comprehensive optimization considering multiple design aspects simultaneously, and the possible barriers that need to be removed to achieve this goal.

Optical Networks-on-Chip (ONoCs) are a promising solution for high-performance multi-core integration with better latency and bandwidth than traditional Electrical NoCs. Wavelength-routed ONoCs (WRONoCs) offer yet additional performance guarantees. However, WRONoC design presents new EDA challenges which have not yet been fully addressed. So far, most topology analysis is abstract, i.e., overlooks layout concerns, while for layout the tools available perform Place & Route (P&R) but no topology optimization. Thus, a need arises for a novel optimization method combining both aspects of WRONoC design. In this paper such a method, PSION, is laid out. When compared to the state-of-the-art design procedure, results show a 1.8x reduction in maximum optical insertion loss.

Microfluidic large-scale integration (mLSI) is a promising platform for high-throughput biological applications. Design automation for mLSI has made much progress in recent years. Columba and its succeeding work Columba 2.0 proposed a mathematical modeling method that enables automatic design of manufacturing-ready chips within minutes. However, current approaches suffer from a huge computation load when the designs become larger. Thus, in this work, we propose Columba S with a focus on scalability. Columba S applies a new architectural framework and a straight channel routing discipline, and synthesizes multiplexers for efficient and reconfigurable valve control. Experiments show that Columba S is able to generate mLSI designs with more than 200 functional units within three minutes, which enables the design of a platform for large and complex applications.

Optical network-on-chip (NoC) is a promising platform beyond electronic NoCs. In particular, wavelength-routed optical network-on-chip (WRONoC) is renowned for its high bandwidth and ultra-low signal delay. Current WRONoC topology generation approaches focus on full-connectivity, i.e. all masters are connected to all slaves. This assumption leads to wasted resources for application-specific designs. In this work, we propose CustomTopo: a general solution to the topology generation problem on WRONoCs that supports customized connectivity. CustomTopo models the topology structure and its communication behavior as an integer-linear-programming (ILP) problem, with an adjustable optimization target considering the number of add-drop filters (ADFs), the number of wavelengths, and insertion loss. The time for solving the ILP problem in general positively correlates with the network communication densities. Experimental results show that CustomTopo is applicable for various communication requirements, and the resulting customized topology enables a remarkable reduction in both resource usage and insertion loss.

Continuous-flow microfluidic large-scale integration (mLSI) shows increasing importance in biological/chemical fields, thanks to its advantages in miniaturization and high throughput. Current mLSI is designed manually, which is time-consuming and error-prone. In recent years, design automation research for mLSI has evolved rapidly, aiming to replace manual labor by computers. However, previous design automation approaches used to design each microfluidic layer separately and over-simplify the layer interactions to various degrees, which resulted in a gap between realistic requirements and automatically generated designs. In this paper, we propose a module model library to accurately model microfluidic components involving layer interactions; and we propose a co-layout synthesis tool, Columba, which generates AutoCAD-compatible designs that fulfill all designs rules and can be directly used for mask fabrication. Columba takes plain-text netlist descriptions as inputs, and performs simultaneous placement and routing for multiple layers while ensuring the planarity of each layer. We validate Columba by fabricating two of its output designs. Columba is the first design automation tool that can seamlessly synchronize with the manufacturing flow.

Technological innovations in continuous-flow microfluidics require updated automated synthesis methods. As new microfluidic components and biochemical applications are constantly introduced, the current functionality-based application mapping methods and the fixed-time-slot scheduling methods are insufficient to solve the new design challenges. In this work, we propose a component-oriented general device concept that enables precise description of operations and devices, and adapts well to technological updates. Applying this concept, we propose a layering algorithm together with a mathematical modeling method to synthesize binding and hybrid-scheduling solutions that support both fixed schedule and real-time decisions. We also consider potential chip layout and optimize the number of flow channels among devices to save routing efforts. Experimental results demonstrate that our solution fully utilizes the chip resources and can handle operations with different requirements.

With advancing process technologies and booming Internet of Things markets, millimeter-wave CMOS RFICs have evolved rapidly and been widely applied in recent years. The performance of CMOS RFICs is very sensitive to the chip layout, and a tiny variation of the microstrip length can cause a large impact to the circuit performance. This results in a time-consuming tuning process including much simulation effort for chip design, which becomes the major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method consisting of two phases: 1) global layout generation and 2) iterative validation. In the global layout generation phase, we focus on the most critical constraints such as layout planarity and device connection relations to determine the topology of the final design. This provides a basis for constructing the accurate model in the iterative validation phase. The layouts generated by applying our method can satisfy very stringent routing requirements of microstrip lines, including spacing/noncrossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both performance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout generation time is significantly reduced from weeks to a few minutes.

Continuous-flow microfluidics have evolved rapidly in the last decades, due to their advantages in effective and accurate control. However, complex control results in complicated valve actuations. As a result, sophisticated interactions between control and flow layers substantially raise the design difficulty. Previous work on design automation for microfluidics neglects the interactions between the control and flow layers and designs each layer separately, which leads to unrealistic designs. We propose the first planarity-guaranteed architectural model, and the first physical-design module models for important microfluidic components, which have modelled the interactions between both control and flow layers, while reducing the design difficulty. Based on the above, we propose the co-layout synthesis tool called Columba, which considers the pressure sharing among different valves, and routes channels in an any-angled manner. Experimental results show that complicated designs considering layer interactions can be synthesized for the first time.

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in recent years. Since the performance of CMOS RFICs is very sensitive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to generate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both performance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout generation time is significantly reduced from weeks to half an hour.

In flow-based biochips, peristaltic pumps consisting of valves are essential to generate circulation flow in a mixer. When a peristaltic pump is activated, the related valves for peristalsis are required to be actuated for many times. However, the roles of valves in traditional chips are fixed, and therefore the valves for peristalsis can wear out much faster than the valves for guiding fluid transportation. This could lead to a reduced lifetime of the chip, because the whole chip function can be affected when just a few or even only a single valve wears out. In this paper, we propose a valve-centered architecture with virtual valves, based on which we introduce a valve-role-changing concept to balance the valve actuations. By switching a valve into different roles, microfluidic components such as mixers, storages, and flow channels can be formed dynamically during the assay process, which enables us to balance the utilization of valves, and synthesize designs that support various kinds of operations. Compared with our preliminary work, we further decrease the largest number of valve actuation as well as the number of valves by the revised dynamic device mapping and fluid path routing. For dynamic device mapping, we introduce a virtual-boundary concept to generate devices at better places while connections between devices are still guaranteed. For fluid path routing, we accurately model valve actuation resulting from our valve-actuation-aware routing, and revise the results by rip-up and reroute. In addition to performance, we improve the reliability of our method by assuring fluid paths from devices to chip boundaries. Experiments show that the new method can be eight times better than the traditional method, and outperforms our preliminary work for large cases even with fewer valves.

On flow-based biochips, valves that are used to form peristaltic pumps wear out much earlier than valves for transportation since the former are actuated more often, which leads to a reduced lifetime of the chip. In this paper, we introduce a valve-role-changing concept to avoid always using the same valves for peristalsis. Based on this, we generate dynamic devices from a valve-centered architecture to distribute the valve actuation activities evenly and reduce the largest number of valve actuations with even fewer valves. In addition, we propose in situ on-chip storages, which can overlap with other devices, so that less area is needed compared with dedicated storages on traditional chips. Moreover, our method provides good support for assays requiring different volumes and ratios of samples. Experiments show that compared with traditional designs, the largest number of valve actuations can be reduced by 72.97% averagely, while the number of valves is reduced by 10.62%.

Length-matching is an important technique to balance delays of bus signals in high-performance printed circuit board (PCB) routing. Existing routers, however, may generate very dense meander segments. Signals propagating along these meander segments exhibit a speedup effect due to crosstalk between the segments of the same wire, thus leading to mismatch of arrival times even under the same physical wire length. In this paper, we present a post-processing method to enlarge the width and the distance of meander segments and hence distribute them more evenly on the board so that crosstalk can be reduced. In the proposed framework, we model the sharing of available routing areas after removing dense meander segments from the initial routing, as well as the generation of relaxed meander segments and their groups for wire length compensation. This model is transformed into an ILP problem and solved for a balanced distribution of wire patterns. In addition, we adjust the locations of long wire segments according to wire priorities to swap free spaces toward critical wires that need much length compensation. To reduce the problem space of the ILP model, we also introduce a progressive fixing technique so that wire patterns are grown gradually from the edge of the routing toward the center area. Experimental results show that the proposed method can expand meander segments significantly even under very tight area constraints, so that the speedup effect can be alleviated effectively in high-performance PCB designs.

In this paper, we propose a post-processing framework which iteratively refines the routing results from an existing PCB router by removing dense meander segments. By swapping and detouring dense meander segments the proposed method can effectively alleviate accumulating crosstalk noise, while respecting pre-defined area constraints. Experimental results show more than 85% reduction of the meander segments and hence the noise cost.

Length-matching is an important technique to balance delays of bus signals in high-performance PCB routing. Existing routers, however, may generate dense meander segments with small distance. Signals propagating across these meander segments exhibit a speedup effect due to crosstalks between the segments of the same wire, thus leading to mismatch of arrival times even with the same physical wire length. In this paper, we propose a post-processing method to enlarge the width and the distance of meander segments and distribute them more evenly on the board so that the crosstalks can be reduced. In the proposed framework, we model the sharing combinations of available routing areas after removing dense meander segments from the initial routing, as well as the generation of relaxed meander segments and their groups in subareas. Thereafter, this model is transformed into an ILP problem and solved efficiently. Experimental results show that the proposed method can extend the width and the distance of meander segments about two times even under very tight area constraints, so that the crosstalks and thus the speedup effect can be alleviated effectively in high-performance PCB designs.

Multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS switches. However, few existing literatures have discussed the algorithms required in MTCMOS's back-end tools. In this paper, we propose a switch-routing framework which serially connects the MTCMOS switches without violating the Manhattan-distance constraint. The proposed switch-routing framework can simultaneously maximize the number of MTCMOS switches covered by its trunk path and minimize the total path length. The experimental result based on four industrial MTCMOS designs demonstrates the effectiveness and efficiency of the proposed framework compared to a solution provided by an EDA vendor and an advanced TSP solver.