Demo Data from EDBT 2026 / reviewers in the wild / expert
W. N. Chau
dblp:65/854
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 3Computer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 60% Performance modeling and evaluation · 40% | |
| Computer networks
1 paper |
Internet architecture and protocols · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip › routing algorithms
deflection routing |
0.0 | 1 | 1995 | Design of ATM switch using hypercube with distributed shared input buffers and dedicated output buffers · ICNP 1995 |
Interconnection networks and networks-on-chip
hypercube network |
0.0 | 1 | 1995 | Design of ATM switch using hypercube with distributed shared input buffers and dedicated output buffers · ICNP 1995 |
Interconnection networks and networks-on-chip › routing algorithms
packet routing |
0.0 | 1 | 1995 | Design of ATM switch using hypercube with distributed shared input buffers and dedicated output buffers · ICNP 1995 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 1995 | Design of ATM switch using hypercube with distributed shared input buffers and dedicated output buffers · ICNP 1995 |
Performance modeling and evaluation › network performance analysis
switch performance analysis |
0.0 | 1 | 1995 | Design of ATM switch using hypercube with distributed shared input buffers and dedicated output buffers · ICNP 1995 |
Internet architecture and protocols › ATM networks
ATM switching |
0.0 | 1 | 1995 | Design of ATM switch using hypercube with distributed shared input buffers and dedicated output buffers · ICNP 1995 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | Clone selection programming and its application to symbolic regression
Zhaohui Gan, Tommy W. S. Chow, W. N. Chau |
Expert Syst. Appl. | 3 |
| 2001 | Imprecision Analysis of PSK Modulation by Fuzzy LogicabstractThe performance of a classical phase shift keying (PSK) detector may be degraded by parameter imprecision. This paper analyzes the performance variation of PSK schemes due to imprecision, and models the imprecise parameters as fuzzy numbers. Results illustrate the extent of the performance variation of the PSK schemes due to parameter imprecision in the analysis. M. K. Lee, S. W. Leung, James W. Minett, W. N. Chau, Y. M. Siu, K. T. Ng |
FUZZ-IEEE | 4 |
| 2001 | Estimating the Length of a Radar Shadow in Shadow-feature-enhanced Detection Using a Fuzzy SystemabstractShadow-feature-enhanced radar detection algorithms potentially allow the probability of target detection to be substantially increased when a target casts a radar shadow across a region of clutter beyond it. However, when the length of the radar shadow is not correctly known, much of the potential performance gain may be lost. We demonstrate a method for estimating the length of the radar shadow using a simple fuzzy system. We apply the shadow length estimation to the shadow-feature-enhanced maximum-likelihood constant false alarm rate (ML-CFAR) detector, showing that its performance can be greatly improved when the shadow length is not known a priori. James W. Minett, S. W. Leung, Y. M. Siu, K. T. Ng, W. N. Chau |
FUZZ-IEEE | 5 |
| 1995 | Design of ATM switch using hypercube with distributed shared input buffers and dedicated output buffersabstractWe investigate a dynamic packet routing approach to ATM switch design using a hypercube. An (n+1)-dimensional hypercube is used to implement an N/spl times/N switch, where N=2/sup n/. Cells arriving at input ports are routed towards their destinations in store-and-forward (SAF) manner. In addition to the SAF buffer, each input/output port has a dedicated buffer. A distributed deflection routing algorithm where the routing priority is based on the age of the cells is developed. An interesting feature of the routing algorithm is that the store-and-forward buffers and the input buffers behave as distributed shared-buffer which effectively smooth out uneven traffic. In addition, our routing algorithm does not suffer from the HOL blocking problem as in the conventional input-output buffered switch architecture. The processing power of each node in the hypercube scales up by a factor of Q(log N) as the network size N is increased. Hence, our approach is suitable for implementing large scale ATM switches. Performance of our design is studied via simulation and found to be better than the conventional input-output buffered nonblocking switch architecture. Derek Chi-Wai Pao, W. N. Chau |
ICNP | 2 |