CC-TEGAS3 is a digital logic simulation system containing subsystems which can perform three different modes of simulation. These modes are used for logic or design verification, worst case timing analysis, and fault simulation. The basic device models are for Boolean gates, a wide range of flip-flops and latches, and a number of MOS elements such as transfer gates. A comprehensive list of functional level device models were incorporated into the system and the resulting system is called CC-TEGAS4. This approach was considered advantageous for today's technology, and an absolute necessity for the LSI and VLSI technologies that are forthcoming. This paper is concerned with the problems encountered and some of the techniques used to implement these functional level models, and results obtained in terms of reduction in required computer resources needed to simulate a network utilizing these new models.