Layout-dependent effects (LDEs) are becoming increasingly important as technology node continues to shrink into the regime of FinFET transistors. Prior LDE studies mainly focus on accurate transistor modeling and fast circuit performance evaluations at the early lifetime of a design. Few studies have been performed on the layout dependency of the circuit aging towards the end of life (EOL). This study demonstrates that, due to transistor-level layout-dependent aging (LDA) behaviors, circuit-level timing degradations are greatly impacted by layout configurations, including length of diffusion and oxide spacing. In this paper, we propose the first circuit-level aging mitigation framework to improve the critical-path timing towards the EOL. Our framework features comprehensive LDA evaluations for standard cell timing, which shows that multiple-row height cells lead to worse EOL timing than singlerow height cells due to length-of-diffusion effects. We further propose a min-cost-flow-based placement approach to concurrently allocate the oxide spacing among neighboring standard cells, which generates much better EOL timing than a conventional greedy approach. Experimental results demonstrate that under the concurrent approach in the proposed aging mitigation framework, the total and worst negative slacks for EOL timing are on average reduced by 42% and 25%, respectively.

Pin access has become one of the most difficult challenges for detailed routing in advanced technology nodes, for example, in 14nm and below, for which double-patterning lithography has to be used for manufacturing lower metal routing layers with tight pitches, such as M2 and M3. Self-aligned double patterning (SADP) provides better control on line edge roughness and overlay, but it has very restrictive design constraints and prefers regular layout patterns. This article presents a comprehensive pin-access planning and regular routing framework (PARR) for SADP friendliness. Our key techniques include precomputation of both intracell and intercell pin accessibility, as well as local and global pin-access planning to enable handshaking between standard cell-level pin access and detailed routing under SADP constraints. A pin access–driven rip-up and reroute scheme is proposed to improve the ultimate routability. Our experimental results demonstrate that PARR can achieve much better routability and overlay control compared with previous approaches.

Pin access has become one of the most difficult challenges for detailed routing in 14nm technology node and beyond, where double patterning lithography has to be used for manufacturing lower metal layers with tight pitches. Self-aligned double patterning (SADP) provides better control on the line edge roughness and overlay but it has very restrictive design constraints and prefers regular layout patterns. This paper presents a comprehensive pin access planning and regular routing framework (PARR) for SADP friendliness. Our key techniques include pre-computation of both intra-cell and inter-cell pin accessibility, as well as local and global pin access planning to enable the handshaking between standard cell level pin access and detailed routing under SADP constraints. Our experimental results demonstrate that PARR can achieve much better routability and overlay control compared with previous approaches.

With high normal operating voltages, latchup is an important reliability issue for high-voltage (HV) ICs. Harsh operating environments further deteriorate the transient-induced latchup (TLU) immunity of HV ICs. High immunity against TLU has therefore become an important reliability factor of HV ESD protection circuits. In this work, a novel ESD protection circuit with HV silicon controlled rectifier as the main ESD protection element has been proposed. The new proposed ESD protection circuit has been verified in a 0.5-nm 16-V Bipolar CMOS DMOS process. Experimental results showed that the new proposed ESD protection circuit has high TLU immunity of +220V/-295V and high human body model (machine model) ESD robustness of 4.5 kV (500V) at the same time.