We present a topology-informed inverse rendering approach for reconstructing high-genus surface meshes from multi-view images. Compared to 3D representations like voxels and point clouds, mesh-based representations are preferred as they enable the application of differential geometry theory and are optimized for modern graphics pipelines. However, existing inverse rendering methods often fail catastrophically on high-genus surfaces, leading to the loss of key topological features, and tend to oversmooth low-genus surfaces, resulting in the loss of surface details. This failure stems from their overreliance on Adambased optimizers, which can lead to vanishing and exploding gradients. To overcome these challenges, we introduce an adaptive V-cycle remeshing scheme in conjunction with a re-parametrized Adam optimizer to enhance topological and geometric awareness. By periodically coarsening and refining the deforming mesh, our method informs mesh vertices of their current topology and geometry before optimization, mitigating gradient issues while preserving essential topological features. Additionally, we enforce topological consistency by constructing topological primitives with genus numbers that match those of ground truth using Gauss-Bonnet theorem. Experimental results demonstrate that our inverse rendering approach outperforms the current state-of-the-art method, achieving significant improvements in Chamfer Distance and Volume IoU, particularly for high-genus surfaces, while also enhancing surface details for low-genus surfaces.

Neural representations for 3D meshes are emerging as an effective solution for compact storage and efficient processing. Existing methods often rely on neural overfitting, where a coarse mesh is stored and progressively refined through multiple decoder networks. While this can restore high-quality surfaces, it is computationally expensive due to successive decoding passes and the irregular structure of mesh data. In contrast, images have a regular structure that enables powerful super-resolution and restoration frameworks, but applying these advantages to meshes is difficult because their irregular connectivity demands complex encoder–decoder architectures. Our key insight is that a geometry image–based representation transforms irregular meshes into a regular image grid, making efficient image-based neural processing directly applicable. Building on this idea, we introduce our neural geometry image–based representation, which is decoder-free, storage-efficient, and naturally suited for neural processing. It stores a low-resolution geometry-image mipmap of the surface, from which high-quality meshes are restored in a single forward pass. To construct geometry images, we leverage Optimal Transport (OT), which resolves oversampling in flat regions and undersampling in feature-rich regions, and enables continuous levels of detail (LoD) through geometry-image mipmapping. Experimental results demonstrate state-of-the-art storage efficiency and restoration accuracy, measured by compression ratio (CR), Chamfer distance (CD), and Hausdorff distance (HD).

Logic locking is an effective approach for protecting integrated circuits against security threats such as Intellectual Property (IP) piracy and malicious design modifications. To defeat SAT attacks, state-of-the-art locking schemes, which are typically constructed using point-function that remains constant when the correct key is applied, while producing a wrong output only under a specific input pattern if an incorrect key is provided. Although this significantly increases the effort required for SAT attack, it introduces a new vulnerability that can be exploited to discover SAT-resilient blocks. Our observation is that pointfunction can lead to control signals, which exhibit significantly lower switching probability and yield clues for identifying anti-SAT cones. This work aims to reveal such clues at the level of FPGA netlist, where switching behavior characteristics can be quantified using the initialization vectors of Look-up-Tables (LUTs). We leverage the switching behavior measurements of LUTs to pinpoint signals with extremely low switching activity to locate control signals associated with SAT-resilient blocks. By forcing the identified control signals to a constant value, the protective function of the SAT-resilient blocks can be neutralized. We validate our attack method on locked circuits with anti-SAT enhancement. Experimental results on six compound logic locking schemes yield an average attack success rate of 99.6% and 100% key recovery rate for each neutralized circuit.

Animating 3D head meshes using audio inputs has significant applications in AR/VR, gaming, and entertainment through 3D avatars. However, bridging the modality gap between speech signals and facial dynamics remains a challenge, often resulting in incorrect lip syncing and unnatural facial movements. To address this, we propose OT-Talk, the first approach to leverage optimal transportation to optimize the learning model in talking head animation. Building on existing learning frameworks, we utilize a pre-trained Hubert model to extract audio features and a transformer model to process temporal sequences. Unlike previous methods that focus solely on vertex coordinates or displacements, we introduce Chebyshev Graph Convolution to extract geometric features from triangulated meshes. To measure mesh dissimilarities, we go beyond traditional mesh reconstruction errors and velocity differences between adjacent frames. Instead, we represent meshes as probability measures and approximate their surfaces. This allows us to leverage the sliced Wasserstein distance for modeling mesh variations. This approach facilitates the learning of smooth and accurate facial motions, resulting in coherent and natural facial animations. Our experiments on two public audio-mesh datasets demonstrate that our method outperforms state-of-the-art techniques both quantitatively and qualitatively in terms of mesh reconstruction accuracy and temporal alignment. In addition, we conducted a user perception study with 20 volunteers to further assess the effectiveness of our approach.

Edge caching in 5G networks shortens latency and alleviates the backhaul. Bringing content from the core network to the caches is a critical issue. When the satellite is integrated with the terrestrial 5G system, an overlay can be formed for cost-efficient content delivery. Multicast delivery over satellite is a promising scheme due to the broadcast nature of the wireless medium and wide coverage. Requests for popular content at nearby times can be aggregated through a multicast stream for bandwidth efficiency. However, directly multicast to a large audience from the satellite suffers from the problems led by fading channels and the flat topologies. The overlay architecture provides new solutions to handle the drawbacks of satellite multicast, e.g., channel and reception diversity, the difficulty of loss recovery and feedback explosion. We explicitly introduce the overlay architecture based on the configuration of multiple multicast groups and the merging of base station clusters for each communication session. The operation of this overlay is further explained. Besides, we also apply network coding to the multicast and cache networks to improve data recovery and bandwidth efficiency. Both theoretical analysis and numerical experiments demonstrate the optimization of network performance.

The rapid development of high-speed railway (HSR) system draws great attention and challenges the current broadband Internet access with high mobility. Though LTE-A networks can provide 100 Mbps throughput within a cell for a train speeding up to 350 km/h, the frequent handovers and service disruptions remain to be handled. This problem is particularly prominent for the delivery of a large volume of contents which demands high throughput and continuous connections. Besides the terrestrial cellular system, a satellite can also provide wireless broadband access with less frequent handovers. Recent advances in low earth orbit (LEO) satellite networks also prove to be practical for content delivery with acceptable delay. Therefore, we present a solution based on the integrated terrestrial-satellite network (ITSN) for high throughput and continuous connectivity. Multipath TCP (MPTCP) protocol is adopted to support multi-bearer communications and we apply network coding to further optimize the performance of MPTCP. Considering the mobility patterns of the HSR and satellite, we propose a scheduling and resource allocation mechanism with the prediction of the handovers and channel situation information (CSI). Cache assisted femto cells are implemented to aggregate the traffic demands and proactively cache the requested contents. Numerical results demonstrate that our solution well resists to the dynamic network conditions and improves the network performance and content delivery efficiency.

Static Random Access Memory (SRAM) is a core technology for building computing hardware, including cache memory, register files and field programmable gate array devices. Hence, SRAM reliability is essential to guarantee dependable computing. While significant research has been conducted to develop automated test algorithms for detecting manufacture-induced SRAM faults, they cannot ensure detection of faults deliberately implemented in the SRAM array by untrusted parties in the integrated circuit development flow. Indeed, such hardware Trojan attacks represent an emerging security threat. While a growing body of research addresses Trojan designs in logic circuits, little research has explored hardware Trojan attacks in embedded memory arrays [20]. In this article, we propose a new class of hardware Trojans targeting embedded SRAM arrays. The Trojans are designed to evade industry standard post-manufacturing tests while enabling attacks targeting various system hardware components during deployment. Transistor-level simulation results demonstrate minimal impact on SRAM power, performance, and stability while Trojans are not activated. We also prove the feasibility of Trojan insertion in foundries by showing the proposed layouts that preserve the SRAM cell footprint and incur zero silicon area overhead. Finally, we elaborate on several system-level attacks that can leverage these Trojans to compromise security and privacy.

Wireless services have been extended from connection-centric to content-centric and this brings rapid increasing data traffic. Considering the concurrent multiple requests for popular contents, multicast is a promising delivery scheme to exploit content reuse. Satellite multicast is superior to others due to the coverage. When terrestrial base stations (BSs) are integrated with the satellite, cooperative transmission is then enabled to handle the fading satellite channels as well as maximize data throughput. Therefore, this paper proposes a co-operative multicast scheme for content delivery in the integrated terrestrial-satellite networks (ITSN) which is further enhanced by network coding. To exploit bandwidth of both terrestrial base stations (BSs) and the satellite, this cooperative multicast scheme uses two-phase transmission. The satellite multicast contents to subscribers in an opportunistic manner with real-time data rate adaptation. Then terrestrial BSs retransmit the lost packets for reliable transmission. Ground users are allocated to subgroups for the channel diversities while network coding is applied to packet loss recovery with fewer retransmissions. Sufficient numerical results demonstrate the enhancement on network throughput brought by the cooperative multicast scheme.

The rapid growth in multimedia applications over cellular networks calls for multicast services. Multicast is an efficient means of delivering contents to multiple users while efficiently utilizing network resources. Layered streaming, e.g., scalable video coding (SVC) provides an excellent solution to handle channel diversities in wireless multicast. This paper presents a cooperative multicast scheme for scalable video content delivery in D2D-enabled heterogeneous cellular networks (HetNets). To extend the multicast service beyond base stations (BSs), D2D links are used to help relay content for cellular multicast. Network coding (NC), implemented through random linear network coding (RLNC) with unequal error protection (UEP) is incorporated in layered contents to enhance reliability and throughput. This paper tries to optimize the multicast scheduling procedures, aiming to assign the optimal modulation and coding schemes (MCSs) for transmissions. The constraints on cache size, backhaul capacity and channel fading are comprehensively considered. Besides, this paper also presents a interference-aware approach for D2D link selection in order to further improve the cooperative multicast. Sufficient numerical results have demonstrated the improvement brought by the proposed scheme significantly on the content delivery efficiency as well as quality of experience (QoE).

The introduction of adaptive coding and modulation (ACM) in DVB-S2 improves system capacity. Transmission mode is adapted to receiving conditions which are fed back through return link supported in DVB-RCS2. A big challenge is that ACM scheme has to follow channel variations which are faster than the delay between channel measurement and feedback reception. Channel state information (CSI) for next transmission often differs profoundly from current estimated result. This causes the mismatch between transmission mode and channel quality. To resolve this problem, this paper deploys a CSI prediction framework and implements machine learning (ML) algorithms for accuracy. Compared with conventional prediction algorithms, ML algorithms have advantage on handling the complicate and changeable time series. In ACM scheme, MODCOD selection is based on channel SNR and MODCOD SNR threshold. Therefore, this prediction work takes channel SNR for next transmission as the prediction target and past SNR plus other correlated information as the prediction basis. To verify prediction accuracy, this paper discusses major factors impacting channel situation in detail and proposes a synthesis channel fading model. Numerical experiment results demonstrate the improvement on system performance while the efficiency and complexity of different commonly-used ML algorithms are also included.

Hardware information flow analysis detects security vulnerabilities resulting from unintended design flaws, timing channels, and hardware Trojans. These information flow models are typically generated in a general way, which includes a significant amount of redundancy that is irrelevant to the specified security properties. In this work, we propose a property specific approach for information flow security. We create information flow models tailored to the properties to be verified by performing a property specific search to identify security critical paths. This helps find suspicious signals that require closer inspection and quickly eliminates portions of the design that are free of security violations. Our property specific trimming technique reduces the complexity of the security model; this accelerates security verification and restricts potential security violations to a smaller region which helps quickly pinpoint hardware security vulnerabilities.

Embedded memory, typically implemented with Static Random Access Memory (SRAM) technology, is an integral part of modern processors and System-on-Chips (SoCs). The reliability and integrity of embedded SRAM arrays are essential to ensure dependable and trustworthy computing. In the past, significant research has been conducted to develop automated test algorithms aimed at comprehensively detecting SRAM faults. While such tests have advanced our ability to detect manufacturing imperfection induced faults, they cannot ensure detection of deliberately implemented design modifications, also known as hardware Trojans, in an SRAM array by untrusted entities in the design and fabrication flow. Indeed, these attacks constitute an emerging concern, since they can affect the integrity of fabricated ICs and cause severe consequences in the field. While a growing body of research addresses Trojan attacks in logic circuits, little to no research has explored these attacks in embedded memory arrays. In this paper, for the first time to our knowledge, we propose a new class of hardware Trojans targeting embedded SRAM arrays. The Trojans are designed to evade industry standard post-manufacturing memory tests (e.g. March test) while enabling targeted data tampering after deployment. We demonstrate various forms of Trojan circuits in SRAM that cause diverse malicious effects and have diverse activation conditions while incurring minimal overhead in power, performance, and stability. Further, the proposed layouts preserve the SRAM cell footprint and incur negligible silicon area overhead.

Security is becoming an increasingly important parameter in current system-on-chip (SoC) design due to diverse hardware security attacks that can affect manufacturers, system designers or end users. To effectively address the security issues, design-time considerations, e.g. incorporation of design-for-security (DfS) features, are becoming essential. However, DfS measures for diverse security threats require specific design modifications to achieve target security level, which significantly increases design effort thus time-to-market, and usually incurs considerable design overhead. In addition, the general heterogeneous architecture of current SoCs makes many core-level DfS mechanisms unusable at SoC level. In this paper, we propose a centralized on-chip infrastructure IP for SoC security (IIPS), which alleviates the SoC designers from separately addressing different security issues through design modifications in multiple cores. It also provides ease of integration and functional scalability. We consider a specific implementation of IIPS that provides protection against: (1) scan-based attack for information leakage through low-overhead authentication; (2) counterfeiting attacks through integration of a Physical Unclonable Function (PUF); and (3) hardware Trojan attacks through a test infrastructure fortrust validation. To make the IP amenable for plug-and-play during SoC design, working protocols of the security functions are designed to comply with IEEE 1500 Standard for Embedded Core Test (SECT). Since IIPS resides outside the functional modules, it does not incur functional performance or power overhead. Simulations and experiments on example SoC designs validate the effectiveness of IIPS in providing protections against diverse attacks at a low hardware overhead.

Counterfeit chips in a supply chain have emerged as a major security concern in the semiconductor industry with serious potential consequences (such as performance degradation, revenue, and reputation loss). With rising incidences of this attack, wide-spread effort has been made in both industry and academia to develop effective countermeasures. However, existing solutions to protect against these attacks suffer from both robustness issue (in terms of detecting chips with minor functional/structural deviations) as well as design/area overhead and test cost. In addition, they cannot reliably detect different forms of cloning attacks. In this paper, we propose a novel characterization method to identify counterfeit chips - in particular, the cloned ones - based on extraction of scan path delay signatures of a chip. It uses the scan chain, a prevalent design-for-testability structure, to create a robust authentication signature. The proposed approach has two major advantages: 1) it comes at virtually zero design and hardware overhead, since it does not require any additional embedded structure; and 2) it alleviates the design house from characterizing each manufactured chip instance, thus mitigating test cost. In addition, a novel and practical method based on clock phase sweep is proposed to measure delay of short scan paths with high resolution. Using Monte Carlo simulation on the layouts of two ISCAS-89 benchmarks at 45-nm CMOS process, we observe that over 99% of counterfeit chips can be reliably identified even under large process variations. Effectiveness of the approach is also validated with delay measurements in field programmable gate array chips.

Side-channel attack (SCA) is a method in which an attacker aims at extracting secret information from crypto chips by analyzing physical parameters (e.g. power). SCA has emerged as a serious threat to many mathematically unbreakable cryptography systems. From an attacker's point of view, the difficulty of mounting SCA largely depends on Signal-to-Noise Ratio (SNR) of the side-channel information. It has been shown that SNR primarily depends on algorithmic and circuit-level implementation, measurement noise, as well as device thermal noise. However, to the best of our knowledge, there has not been any study on the effect of power delivery network (PDN) on SCA resistance. We note that the PDN plays a significant role in SNR of measured supply current. Furthermore, SCA resistance strongly depends on the operating frequency due to RLC structure of a power grid. In this paper, we analyze the effect of power grid on SCA and provide quantitative results to demonstrate the frequency-dependent SCA resistance due to PDN-induced noise. This property can potentially be exploited by an attacker to facilitate the attack by operating a device at favorable frequency points. On the other hand, from a designer's perspective, one can explore countermeasures to secure the device at all operating frequencies while minimizing the design overhead. Based on this observation, we propose a frequency-dependent noise-injection based compensation technique to efficiently protect against SCA. Simulation results using realistic PDN model as well as experimental measurements using FPGA test board validate the observations on role of PDN in SCA and the efficacy of the proposed compensation approach.

Many industrial systems, sensors and advanced propulsion systems demand electronics capable of functioning at high ambient temperature in the range of 500-600°C. Conventional Si-based electronics fail to work reliably at such high temperature ranges. In this paper we propose, for the first time, a high-temperature reconfigurable computing platform capable of operating at temperature of 500°C or higher. Such a platform is also amenable for reliable operation in high-radiation environment. The hardware reconfigurable platform follows the interleaved architecture of conventional Field Programmable Gate Array (FPGA) and provides the usual benefits of lower design cost and time. However, high-temperature operation is enabled by choice of a special device material, namely silicon carbide (SiC), and a special switch structure, namely Nano-Electro-Mechanical-System (NEMS) switch. While SiC provides excellent mechanical and chemical properties suitable for operation at extreme harsh environment, NEMS switch provides low-voltage operation, ultra-low leakage and radiation hardness. We propose a novel multi-layer NEMS switch structure and efficient design of each building block of FPGA using nanoscale SiC NEMS switches. Using measured switch parameters from a number of SiC NEMS switches we fabricated, we compare the power, performance and area of an all-mechanical FPGA with alternative implementations for several benchmark circuits.

Various design-for-security (DFS) approaches have been proposed earlier for detection of hardware Trojans, which are malicious insertions in Integrated Circuits (ICs). In this paper, we highlight our major findings in terms of innovative Trojan design that can easily evade existing Trojan detection approaches based on functional testing or side-channel analysis. In particular, we illustrate design and placement of sequential hardware Trojans, which are rarely activated/observed and incur ultralow delay/power overhead. We provide models, examples, theoretical analysis of effectiveness, and simulation as well as measurement results of impact of these Trojans in a hardened design. It is shown that efficient design and placement of sequential Trojan would incur extremely low side-channel (power, delay) signature and hence, can easily evade both post-silicon validation and DFS (e.g. ring oscillator based) approaches.