Effect-Cause diagnosis procedures are used to diagnose failing dies and improve manufacturing yield. Several methods have been proposed to accelerate Effect-Cause diagnosis procedures by utilizing a small-sized fault signature dictionary. Recently, pre-silicon diagnosis simulation has been proposed to identify quality issues in diagnosis before silicon volume production. Asymmetric Partition Trees (APT) have been proposed to extract useful information in the fault dictionary for diagnosis simulation applications. APT has proven to have a minimum tree size. In this paper, we propose using fault group information in APT to distribute the fault signature dictionary across APT tree nodes. With APT, the small fault signature dictionary can be further reduced, thereby improving diagnosis performance. The larger the designs, the greater the savings.

Diagnosis simulation based on stuck-at faults cannot expose all chain diagnosis problems because silicon defects don’t behave exactly as stuck-at faults. For chain failures, the fault effect can be activated during scan shift cycles and capture cycles in scan test patterns. The activation conditions of silicon defects are generally more complex and do not activate the fault effect in all cycles. To accurately estimate diagnosis coverage during chain diagnosis simulation, this paper proposes using distinguishing bits. Distinguishing bits, which are simulation-failing bits of one fault but not simulation-failing bits of another fault, are used in this paper to distinguish each silicon defect from others. The chain diagnosis quality of silicon defects can be improved by increasing the distinguishing bits of all scan cell faults. Specific diagnosis test patterns are proposed to increase the number of distinguishing bits of each fault. If the diagnosis test patterns cannot be created, adaptive diagnosis points are proposed to modify the designs to facilitate the creation of these diagnosis test patterns.

Diagnosis of defects on scan chains is the established methodology for improving semiconductor manufacturing yield throughout the production cycle. The best possible result is to obtain a perfect diagnosis resolution, i.e. identifying a single scan cell per defect. With increased structural complexity and emergence of new production technologies, like backside power, there is a need to improve diagnosis callout beyond single-cell to include transistor-level visibility. In this paper we will present a novel end-to-end software-based methodology for enhancing scan chain diagnosis resolution with cell aware information. The new diagnosis methodology enables the isolation of defects in control signals local to multi-bit register arrays. Volume diagnosis benchmarks and silicon data will be shown to present suspect area improvements that will allow for faster physical failure analysis (PFA) turnaround times.

A pre-silicon design-for-diagnosis flow is a critical step in IC manufacturing. It is the key to achieving high diagnosis quality, which is necessary to improve yield and meet time-to-volume business requirements. This paper introduces a novel mechanism that significantly enhances this process. By inserting an XOR gate at scan cells, we enable these cells to operate in an additional mode, thereby improving their diagnosability. The activation of this extra mode is facilitated by a combination of a diagnosis-enable signal bit and the scan-enable signal. A key aspect of our approach is using a local scan cell without an additional input pin to provide the diagnosis-enable signal, a practical innovation that enhances the efficiency of the manufacturing process.

Scan diagnosis has long been relied upon to provide localized defect suspects for a failing die using failing test cycle information for that die and design data. These suspects from scan diagnosis have been used to drive failure analysis (FA) to find the root cause of manufacturing yield loss. The fewer suspects that scan diagnosis produces (higher diagnosis resolution), the quicker and more efficient the FA cycle time. The gains observed are mainly due to the reduced need for fault isolation for these highly resolved diagnosis reports. Identifying design or test pattern related bottlenecks to diagnosis resolution earlier in the design cycle can be useful to anticipate the impact of a particular design on yield learning. In the technique described in this paper, we show how diagnosis resolution can be estimated from design data for both chain and logic defects. The detailed comparison of diagnostic metrics and resolution statistics from simulation and silicon results are presented. Overall, we observe strong correlation in the predicted resolution metrics and diagnosis quality.

Reversible scan chain is an architecture targeted towards improving the quality of chain diagnosis. In this scan architecture, chains are designed to shift the test data in both directions to isolate a defect. We implemented this technique on a test chip in one of the most advanced technology nodes to measure its benefit over its cost. Test chips are typically low in volume and may suffer from worse diagnosis resolution and lower diagnosis convergence than production chips due to early process technology. Hence, it is very important to enhance diagnosis resolution and increase successful diagnosis data volume without losing accuracy to help expedite yield learning. In this paper, the detailed evaluation method together with silicon data and failure analysis results are presented. Moreover, we utilize this novel methodology for improving diagnostics suspect resolution and physical area. Overall, we observe significant benefit in diagnosis quality. Specifically, 4X improvement in the number of suspects and up to 7X improvement in suspect cell area is observed without losing accuracy. Design overhead is also presented and discussed.

Diagnosis becomes a much more prevalent factor in the successful fabrication process of a design. In order to keep up with continuously shrinking technology nodes, compression along with compaction techniques became a standard methodology allowing to control the cost of test. Typically compaction techniques focus on detectability thus maintaining high quality of test, but neglect or, in many cases, ignore their impact on diagnosis. This paper presents a compactor which allows significantly improving chain diagnosis resolution while maintaining high quality standards from detectability point of view and having virtually no impact on test time and logic diagnosis. The paper presents the X-press compactor which is driven in a way allowing to maximize diagnostic ability of chain failures. Specifically, the number of physical failure analysis-ready cases increased up to two times. The feasibility and efficiency of the proposed solution is confirmed by a number of experimental results performed for industrial designs, including actual chain diagnosis.

The following topics are dealt with: integrated circuit testing; fault diagnosis; integrated circuit design; logic testing; logic design; system-on-chip; design for testability; learning (artificial intelligence); field programmable gate arrays; IEEE standards.

This paper presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip (SoC) designs with embedded test data compression. These designs pose significant challenges to the channel management scheme, flow, and tools. This paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with embedded deterministic test-based test data compression. The same solutions allow efficient handling of physical constraints in realistic applications. Finally, state-of-the-art SoC test scheduling algorithms are rearchitected accordingly by making provisions for: 1) setting up time-effective test configurations; 2) optimization of SoC pin partitions; 3) allocation of core-level channels based on scan data volume; and 4) more flexible core-wise usage of automatic test equipment channel resources. A detailed case study is illustrated herein with a variety of experiments allowing one to learn how to tradeoff different architectures and test-related factors.

The paper presents a high-speed serial interface between external tester and Embedded Deterministic Test (EDT) compression logic hosted by SoC designs. With only a single bidirectional link, the system is capable of feeding distributed heterogeneous cores with hundreds of test channels. Moreover, it synergistically supports EDT bandwidth management to improve the overall test performance. A detailed study indicates a high potential of the serial EDT approach to handle large multicore SoC designs by deploying only a single serial interface and completing the entire test for stuck-at faults in less than one second. Experiments conducted with the help of FPGA -- based evaluation platform confirm feasibility and a high effectiveness of the proposed solution.

Due to a production error, an incorrect figure was used for Fig. 8 on p. 1781 in the above paper (ibid., vol. 32, no. 11, pp. 1776-1786, Nov. 2013). The correct figure is presented here.

The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.

This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein.

This paper presents novel methods of enhancing test compression solutions for SoC designs. The ability of the proposed schemes to improve the encoding efficiency, test compression, and test time is accomplished by either appropriate selecting or laying out ATE channel injectors within EDT-based decompressors. The efficacy of new techniques with respect to test bandwidth management is demonstrated by running experiments on several industrial SoC designs and is reported herein.

This paper presents preemptive test application schemes for system-on-a-chip (SoC) designs with embedded deterministic test-based compression. The schemes seamlessly combine new test data reduction techniques with test scheduling algorithms and novel test access mechanisms devised for both input and output sides. In particular, they allow cores to interface with automatic test equipment through an optimized number of channels. They are well suited for SoC devices comprising both nonisolated cores, i.e., blocks that occasionally need to be tested simultaneously, and completely wrapped modules. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application schemes and are reported herein.

Growing test data volume and excessive test power consumption in at-speed scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power in at-speed delay test utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the test time. Reduced test data volume can be expected to permit fewer tester channels for testing which can increase the number of chips tested in parallel. Experimental results for a set of industrial circuits show that the proposed method, on average, reduces test data volume by a factor 2.7, switching activity during scan shift by a factor of 5 and peak switching activity during test response capture by a factor of 2.

The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output sides. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application scheme and are reported herein.

The paper presents a preemptive test application scheme for system-on-chip (SoC) designs with EDT-based compression. It seamlessly combines a new test data reduction technique with a test scheduling algorithm and a novel test access mechanism. It is particularly well suited for SoC devices comprising non-isolated cores, i.e., blocks that occasionally need to be tested simultaneously.