This paper presents SPIDER, a novel methodology that advantageously utilizes metal fill to simultaneously fulfil metal density requirements and reduce IR-drop of the power distribution network. This is achieved through the addition of partially redundant connections between metal fills and power meshes. Our technique is especially significant for 90nm process technology or below because (1) metal fill must now be done as part of the IC implementation flow due to its increasing impact on timing, (2) the tolerance for IR drop is tightening due to voltage scaling, and the increasingly conservative power mesh design to address IR-drop is adding significant burden on the available routing resources, (3) IR-drop is getting worse due to increasing design sizes, and (4) the large degree of design uncertainty demands IRdrop repair capabilities that can be applied after routing is completed. SPIDER addresses all these issues practically with little or no cost. Experimental results further demonstrated the robustness and effectiveness of our approach: SPIDER achieves an average IR-drop reduction of 62.2% in 16 designs of various sizes.

Using workstations on a LAN as a parallel computer is becoming increasingly common. At the same time, parallelizing compilers are making such systems easier to program. Understanding the traffic of compiler-parallelized programs running on networks is vital for network planning and designing quality of service systems. To provide a basis for such understanding, we measured the traffic of six dense-matrix applications written in a dialect of High Performance Fortran, compiled with the Fx parallelizing compiler, and run on an Ethernet LAN. The traffic of these programs is profoundly different from typical network traffic. In particular the programs exhibit global collective communication patterns, correlated traffic along many connections, constant burst sizes, and periodic burstiness with bandwidth dependent periodicity. The traffic of these programs can be characterized by the power spectra of their instantaneous average bandwidth.

Given an undirected graph G=(V, E) with positive edge weights (lengths) /spl omega/: E/spl rarr//spl Rfr//sup +/, a set of terminals (sinks) N/spl sube/V, and a unique root node e/spl epsiv/N, a shortest path Steiner arborescence (hereafter an arborescence) is a Steiner tree rooted at, spanning all terminals in N such that every source-to-sink path is a shortest path in G. Given a triple (G, N, r), the minimum shortest path Steiner arborescence (MSPSA) problem seeks an arborescence with minimum weight. The MSPSA problem has various applications in the areas of physical design of very large-scale integrated circuits (VLSI), multicast network communication, and supercomputer message routing; various eases have been studied in the literature. In this paper, we propose several heuristics and exact algorithms for the MSPSA problem with applications to VLSI physical design. Experiments indicate that our heuristics generate near optimal results and achieve speedups of orders of magnitude over existing algorithms.

Given an undirected graph G = (K E) with positive edge weights (lengths) w : E + R+, a set of terminals (sinks) N C V, and a unique root node r E N, a shortest-path Ste%er arborescence (simply called an arborescence in the following) is a Steiner tree rooted at T spanning all terminals in N such that every source-to-sink path is a shortest path in G. Given a triple (G, N, T), the Minimum Shortest-Path Steiner Arborescence (MSPSA) problem seeks an arborescence with minimum weight.The MSPSA problem has various applications in the areas of VLSI physical design, multicast network communication, and supercomputer message routing; various cases have been studied in the literature.In this paper, we propose three efficient heuristics for the MSPSA problem and present applications to VLSI physical design.Experiments indicate that our algorithms generate near-optimal results and achieve speedups of several orders of magnitude over existing algorithms.1.

In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions. This relation leads to a polynomial time algorithm for computing the lower and upper bounds of the optimal SBWS solutions, which enables an efficient optimal algorithm for computing optimal SBWS solutions. We have applied the SBWS algorithms to the clock nets in a spread spectrum IF transceiver chip and HSPICE simulations show that our algorithms can reduce skew and power by a factor of 3.5X and 2.6X, respectively, when compared to the manual layout of the clock nets in the original chip.

In this paper, we study the optimal wiresizing problem under the Elmore delay model. We show that the optimal wiresizing solutions satisfy a number of interesting properties, including the separability, the monotone property, and the dominance property. Based on these properties, we have developed a polynomial-time optimal wiresizing algorithm for arbitrary interconnect tree structures under Elmore delay model. Extensive experimental results have shown that our wiresizing solution reduces interconnect delay by up to 51% when compared to the uniform-width solution of the same routing topology. Furthermore, compared to the wiresizing solution based on a simpler RC delay model our wiresizing solution reduces the total wiring area by up to 28% while further reducing the interconnect delays to the timing-critical sinks by up to 12%.>

In this paper, we study the interconnect design problem under pared to those by the best known Steiner tree algorithm.

We study the optimal wiresizing problem under the distributed Elmore delay model. We show that the optimal wiresizing solutions satisfy a number of interesting properties, including the separability, the monotone property, and the dominance property. Based on these properties, we develop a polynomial-time optimal wiresizing algorithm for arbitrary interconnect structures under the distributed Elmore delay model. Extensive experimental results show that our wiresizing solution reduces interconnection delay by up to 51% when compared to the uniform-width solution of the same routing topology. Furthermore, compared to the wiresizing solution based on a simpler RC delay model in our wiresizing solution reduces the total wiring area by up to 28% while further reducing the interconnection delays to the timing-critical sinks by up to 12%.