This paper presents two timing window methodologies used in UltraSPARC-IIIi/spl trade/ microprocessor design. They have improved the accuracy of timing and noise analysis. In timing analysis, timing windows are applied to calculate effective Miller factors of coupling nets; in noise analysis, they are applied to waive false noise violations. Results show that by using timing windows in timing analysis, 72% of the CPU-level nets have more accurate Miller factors. Thus, it reduces the number of false timing paths. During the development of this application, a simple and practical convergence rule is defined to stop the iteration. Also, the timing window application on noise analysis has identified 42% of the CPU-level noise violations which can be waived in UltraSPARC-IIIi/spl trade/ chip. This significantly improved the productivity of the design.

Architecture-level power estimation has received more attention recently because of its efficiency. This article presents a technique used to do power analysis of processors at the architecture level. It provides cycle-by-cycle power consumption data of the architecture on the basis of the instruction/data flow stream. To characterize the power dissipation of control units, a novel hierarchical method has been developed. Using this technique, a power estimator is implemented for a commercial processor. The accuracy of the estimator is validated by comparing the power values it produces against measurements made by a gate-level power simulator for the same benchmark set. Our estimation approach is shown to provide very efficient and accurate power analysis at the architecture level. The energy models built for first-pass estimation (such as ALU, MAC unit, register files) are reusable for future architecture design modification. In this article, we demonstrate the application of the technique. Furthermore, this technique can evaluate various kinds of software to achieve hardware/software codesign for low power.

This paper presents a technique used to do po wer analysis of a real p rocessor at the architectural lev el. The target processor in tegrates a 16-bit DSP an d a 32-bit RISC on a single c hip. O ur po wer estimator pro vides po wer consumption data of the architecture based on the instruction/data flo w stream We demonstrat e the accuracy of the estimator by com paring the po wer valu es it p roduces against measurem en tsm adeby a gate level po wer sim ulator for th e same benc hmark set. Our estimation approac h has been shown to pro vide v ery efficient accurate pow er an alysis at the architectural level.

The energy consumption of a system depends upon the hardware rutd software component of a system.Since it is the software which drives the hardware in most systems.decisions taken during software design has significant impact on the energy consumption of the processor.The paper focuses on decreasing energy consumption of o processor using software techniques.A novel compiler technique is proposed which Educes energy consumption by proper register labeling during the compilation phase.The idea behind this technique is to reduce the energy of the processor by reducing the energy of the instruction register (also the instruction data bus) and the register file decoder by encoding the register labels such that the sum of the switching costs between all the register labels in the tmnsition graph is minimized.There is no hardware pen&y since this is purely a compiler optimization.Results on benchmarks show that the energy consumption of the DLX processor can be.reduced by 9.82% (maximum) and 4.25% (avenge) (as measured by DLX energy simulator).In addition seveml compiler techniques such os loop unrolling, software pipelining, recursion elimination and of effects of different algorithms on power and energy consumption are studied.This evaluation methodology is usefid for computer architects to evaluate energy improvements of their hardware, compiler writers to evaluate energy of the compiled code nnd program writers to evaluate energy of data structures and algodhltls.v---e.?_ .