This paper explores technology-circuit co-design techniques that leverage the heterogeneous integration of ad-vanced SiGe BiCMOS and deeply-scaled CMOS. We introduce an active bootstrapping concept that extends the bandwidth of a track-and-hold (T&H) front end to several tens of GHz (> 20 GHz), while preserving high spectral purity (> 55 dB across the entire band) and consuming low power. The proposed techniques are demonstrated through circuit simulations of a die stack featuring 130 nm SiGe BiCMOS and 22 nm FDSOI. Using 4x time-interleaving, the T&H front end achieves up to 22 GS/s sample rate, a bandwidth above 20 GHz, an IM3 better than -60 dB (up to 20 GHz), and a power consumption of 150 mW. For comparison, simulation results of a single-die 22 nm FDSOI front end are also provided.

A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapath model is introduced that allows maximum flexibility in scheduling bus transfers independent of operation scheduling. A novel integer linear programming (ILP) formulation that optimally selects and assigns data-transfers to busses while scheduling the bus transfers to minimize a linear combination of the number of busses, bus loading in terms of tristate drivers and fanout, registers and register file storage (RAM) locations. We demonstrate that our resulting optimal datapaths compare favorably to others for signal processing synthesis benchmarks such as: single and multiple elliptic filter and fast discrete-cosine-transform (FDCT).

This paper presents a floorplanner for datapath with the capability of re-allocating data storage for minimizing the interconnect area and critical path delay without altering the number of functional units and the schedule. The tool has combined two novel approaches: 1-A placement and routing model to handle different architectural topologies (mux. and/or bus based) suitable for FPGA's. 2-An efficient formulation for the binding of register/interconnect and combined floorplanning. The complexity of the architectural and floorplanning model, and of the cost function, have led us to the use of a stochastic optimization process. The running time of the whole process indicates the viability of the method. We show through various examples how the floorplanner improves the area and critical path delay of the datapath compared to a plain floorplanner. The improvement is about 20% for the critical path delay when this objective is a stringent constraint.

A novel integer linear programming (ILP) formulation for optimally mapping a partitioned signal processing algorithm on a multiple FPGA board is presented. Our approach performs all the following synthesis bindings simultaneously: operation scheduling, function unit allocation, interconnections, data-transfer scheduling between FPGAs, and input/output port allocation. Moreover, we present architectural models suitable for multiple FPGA boards and account for limitations in the structure of interconnections of multiple FPGAs. We demonstrate the quality of the results of our approach for typical signal processing synthesis benchmarks, including the difficult examples of discrete and inverse discrete cosine transforms (DCT and IDCT).>

Major applications of CMOS VLSIs require the use of high fan out busses, such as Asynchronous Transfer Mode (ATM) cross-bar switching matrices, high performance processors employing multiple busses, and high performance CPLDs using universal interconnection matrices. The bus interface circuits are major contributors to the power dissipation of a system for achieving high clocking frequencies. To address the increased power dissipation for high speed busses, a novel reduced voltage swing CMOS bus interface circuit is presented here. The design is a combination of drivers and receivers which perform level translation without any need to reduce the supply voltage. The simulation results based on these circuits show significant enhancements on both speed and power in comparison with the conventional CMOS tri-state driver techniques. To further assess this design, an LSI 32/spl times/32 crosspoint switch is implemented to be used for ATM communication systems. The chip uses a 1.2 /spl mu/m CMOS process with a die size of 4/spl times/3 mn, and has pseudo ECL input/output compatible interfaces which can operate at 250 Mb/s serial communication links per channel. The power consumption at 250 Mb/s is 0.6 W which is 60% lower than other published results for a similar switch. Without the input/output pad restrictions, the simulation results indicate that the switching matrix is capable of running at 622 Mb/s with a similar power reduction.>

This paper presents the design methodology of /spl Sigma/-/spl Delta/ ADC that uses a high order single bit first stage, and a multi bit first order second stage and introduces a novel multiplier-less high order digital correction block. The selection of the number of bits and order is done by design graphs that are obtained through numerous simulations under practical tolerances in implementation parameters. By using an example of a 3rd order first stage with a 5-bit second stage, we show that the over-sampling ratio can be reduced to (=16 bits) for 2% mismatch implementation tolerances between analog and digital parts. Our approach results in an overall increase in the maximum baseband frequency, while the additional digital correction logic is minimal.>

This paper presents a novel layout model and floorplanning tool particularly suitable for taking into account user defined layout constraints on specific sets of modules and specific locations. The user defined layout constraints can be the setting of any common topological property associated with a group of specific modules such as the neighboring property for example. Or the use of any topological regularities in a design such as regular bus structure or the use of the structural property such as the bit-sliceable or non bit-sliceable feature of a module set, or their similar shape. The exploitation of these structural information helps in producing more compact layout especially for datapath oriented architectures. Moreover, in addition to the area and total wiring length, the critical path delay is systematically minimized through a global cost function. The potential candidates for the critical path computation can be specifically defined by the user. The core of the optimization process is based on simulated annealing.>

Accurate and fast time-domain current waveform simulation is important for the design of reliable CMOS VLSI circuits. A detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by SPICE LEVEL 3 at peak values and 5% at the average current is presented. The current model accounts for short-channel effects, input risetimes, short-circuit and dynamic current, and circuit topology. Moreover, the model produces piecewise linear current waveforms and can be incorporated in any switch-level simulator. Using the models in an event driven simulator, a 3-4 orders of magnitude speedup relative to SPICE LEVEL 3 has been achieved. The results for current waveform accuracy are better than those obtained for previously published methods and in particular for complex CMOS circuits.>

An automated architectural synthesis methodology for implementing digital neural networks is presented. The synthesis approach uses heuristics and is based on VLSI multiple-bus/functional-unit architectures with internal parallelism. The synthesis methodologies and tradeoffs as well as the features of the architectures are presented. The architectures resulting from the synthesis tool outperform other architectures for the same applications.>

A design methodology for automated mapping of DSP algorithms into VLSI architectures is presented. The methodology takes into account explicit algorithm requirements on throughput and latency, in addition to VLSI technology constraints on silicon area and power dissipation. Algorithm structure, design style of functional units, and parallellism of the architecture are all explored in the design space. The synthesized architecture is a multibus multifunction unit processor matched to the implemented algorithm. The architecture has a linear topology and uses a lower number of interconnects and multiplexer inputs compared to other synthesized architectures with random topology having the same performance. The synthesized processor is a self-timed element externally, while it is internally synchronous. The methodology is implemented in a design aid tool called SPAID. Results obtained using SPAID for two DSP algorithms compare favorably with other synthesis techniques.>

An architectural synthesis methodology for a multibus multifunctional unit processor is presented. It is implemented as part of a design aid tool called SPAID. The input to SPAID is a DSP flow graph algorithm description with the required throughput and latency. The synthesized processor is a self-timed element externally, while it is internally synchronous and suitable for a systolic multiprocessor implementation for large DSP applications. For a benchmark elliptic filter algorithm SPAID synthesizes architectures with a linear topology that use fewer interconnects and multiplexers than other systems synthesizing random-topology architectures for the same throughput.>