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Richard N. Pelavin

dblp:66/1670 · DBLP profile ↗
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5ranked-venue papers
2as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Artificial intelligence and machine learning · 1 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%
Artificial intelligence
1 paper
Knowledge representation and reasoning · 100%
Theoretical computer science
1 paper
Logic in computer science · 70% Automated reasoning and model checking · 30%

Topics — the 11 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
0.021983
Hierarchical Wire Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Hierarchical channel router · DAC 1983
Knowledge, reasoning and agents › Knowledge representation and reasoning › reasoning about action and change
action representation
0.011987
A Model for Concurrent Actions Having Temporal Extent · AAAI 1987
Knowledge, reasoning and agents › Knowledge representation and reasoning › reasoning about action and change
concurrent actions
0.011987
A Model for Concurrent Actions Having Temporal Extent · AAAI 1987
Knowledge, reasoning and agents › Knowledge representation and reasoning
temporal reasoning
0.011987
A Model for Concurrent Actions Having Temporal Extent · AAAI 1987
Logic in computer science
modal logic
0.011986
A formal logic of plans in temporally rich domains · Proc. IEEE 1986
Automated reasoning and model checking
planning
0.011986
A formal logic of plans in temporally rich domains · Proc. IEEE 1986
Logic in computer science
temporal logic
0.011986
A formal logic of plans in temporally rich domains · Proc. IEEE 1986
Electronic design automation › physical design › routing
channel routing
0.011983
Hierarchical channel router · DAC 1983
Electronic design automation › physical design
routing
0.011983
Hierarchical Wire Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › physical design › routing
wire routing
0.011983
Hierarchical Wire Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › physical design › routing › VLSI routing
gate array routing
0.011983
Hierarchical Wire Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983

Methods — techniques the papers use, named apart from their topics

situation calculus · 0.0modal logic · 0.0formal semantics · 0.0hierarchical routing · 0.0
YearPublicationVenuePosition
1987 A Model for Concurrent Actions Having Temporal Extent
Richard N. Pelavin, James F. Allen
AAAI1
1986 A formal logic of plans in temporally rich domains
abstract
This paper outlines a temporal logic extended with two modalities that can be used to support planning in temporally rich domains. In particular, the logic can represent planning environments that have assertions about future possibilities in addition to the present state, and plans that contain concurrent actions. The logic is particularly expressive in the ways that concurrent actions can interact with each other and allows situations where either one of the actions can be executed, but both cannot, as well as situations where neither action can be executed alone, but they can be done together. Two modalities are introduced and given a formal semantics: INEV expresses simple temporal possibility, and IFTRIED expresses counteffactual-like statements about actions.
Richard N. Pelavin, James F. Allen
Proc. IEEE1
1983 Hierarchical channel router
Michael Burstein, Richard N. Pelavin
DAC2
1983 Hierarchical channel router
Michael Burstein, Richard N. Pelavin
Integr.2
1983 Hierarchical Wire Routing
abstract
We propose a new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels. Popularity of gate arrays technologies still remains high among VLSI chip manufacturers and, as the scale of integration grows, the interconnection problem becomes increasingly difficult if not intractable. The same is true for problems of switchbox and channel routing, which usually arise in custom designs; the uniformity of wiring substrate unites them with gate array routing problem. Our approach was initially aimed at gate arrays, but it extends naturally to switchboxes and channels. Uniformity of the wiring substrate is the crucial assumption of the method. It assumes that horizontal and vertical wire segments are realized on different wiring layers and vias are introduced each time a wire changes direction. Any "jogs" ("wrong way" wires) are prohibited. Within these limitations our approach is advantageous over the existing wiring methodologies. Our final layout of wires is independent of both net ordering and ordering of pins within the nets. The wire densities we are able to achieve are often higher than those achieved by other routers. Because of the hierarchical nature of our method it is inherently fast, usually by an order of magnitude faster than the routers based on wave propagation (maze running) technique.
Michael Burstein, Richard N. Pelavin
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2