Demo Data from EDBT 2026 / reviewers in the wild / expert
P. Antognetti
dblp:66/1672
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 1 | 1987 | A Tile-Expansion Router · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Electronic design automation › physical design
routing |
0.0 | 1 | 1987 | A Tile-Expansion Router · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Electronic design automation › physical design › design planning
chip planning |
0.0 | 1 | 1987 | A Tile-Expansion Router · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Methods — techniques the papers use, named apart from their topics
working tree search · 0.0corner stitching data structure · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1989 | A reconfigurable wiring algorithm for three-layer maze routing
Francesco Curatelli, P. Antognetti |
Integr. | 2 |
| 1987 | A Tile-Expansion RouterabstractA router based on a tile-expansion algorithm and corner stitching data structure is presented. This program finds connections with a minimum number of jogs and it ensures that a possible solution will be found. Using a working tree, it allows an exhaustive and recursive search along all available areas for routing. The connections are made going back through the working tree until the starting terminal is reached. There are two Manhattan layers that the user can choose for each direction to implement connections; the router can be used to wire hierarchical blocks using a chip planning methodology. The program has been successfully tested on examples concerning different classes of problems. A. Margarino, A. Romano, Alessandro De Gloria, Francesco Curatelli, P. Antognetti |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 5 |