A tree-driven clock grid has become the choice of clock delivery for most microprocessors, due to its ability to achieve lower skew and lower variability than clock trees, and is becoming the choice of clock delivery for certain high-end application-specific integrated circuit designs. This paper reports on a clock routing tool that was used in designing multiple tree-driven clock grids in a 2.3 GHz processor system-on-chip, which achieved below 5 ps skew within 500$\mu{\rm m}$Manhattan distance and below 10 ps skew across each clock grid. This clock routing tool employs a nonsequential algorithm comprised of linear programming and combinatorial heuristics. Its robust length-matching capability enables flexible buffer placement, improved clock signal quality, and robustness to variations.

This paper compares and contrasts two common clock distribution styles: clock grids, the preferred microprocessor distribution style, and clock trees, the preferred ASICs distribution style. After a high level description of the routing methodologies for clock grids and clock trees, a case study is presented to compare the performance and cost trade-off of grids and trees. Our results show that clock grids consume more power and wiring resources but only to achieve aggressive clock targets. In this example a clock tree style uses 28% less wiring than a full clock grid style but suffers 12 ps more skew. However, compared to a sparse grid style, a clock tree solution uses only 4% less wiring and suffers 9.6 ps higher skew. The key message is that the cost in extra wiring and power consumption across different clock distribution styles is mainly driven by performance targets as opposed to being fundamentally dictated by the grid vs. tree decision.

As the industry moves from single- to multicore processors, the challenges of how to reliably design and analyze power delivery for such systems also arise. We study various workload assignments to cores and their impact on the global power grid noise. We develop metrics to estimate the amount of noise propagated from core to core and propose a power supply noise aware workload assignment method. In our experiments, we show that performance loss can be significant if workload assignment is not properly made.

This work presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node V/sub DD/ net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.

Modern submicron very large scale integration designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on the grid reduces noise margin and increases gate delay, resulting in a serious performance impact. Checking the integrity of the supply voltage using traditional circuit simulation is not practical, for reasons of time and memory complexity. The authors propose a novel multigrid-like technique for the analysis of power grids. The grid is reduced to a coarser structure, and the solution is mapped back to the original grid. Experimental results show that the proposed method is very efficient as well as suitable for both de and transient analysis of power grids.

Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at ever lower voltages. The resulting voltage drop on the grid reduces noise margin and increases gate delay, resulting in a serious performance impact. Checking the integrity of the supply voltage using traditional circuit simulation is not practical, for reasons of time and memory complexity. We propose a novel multigrid-like technique for the analysis of power grids. The grid is reduced to a coarser structure, and the solution is mapped back to the original grid. Experimental results show that the proposed method is very efficient as well as suitable for both DC and transient analysis of power grids.

A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a user-supplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value which can be quite tight (under 10% difference between the two in many cases). As a result, the power dissipation is obtained by simulating only a fraction of the potentially very large vector set.

The decrease in feature size and added chip functionality in large sub-micron integrated circuits demand larger grids for power distribution. Since power grids are performance limiting factors [1, 2, 3], then their analysis is important in order to (1) predict the performance and (2) improve the performance if necessary. Thus, there is a clear need for new efficient, in terms of both execution time and memory, techniques for power grid analysis.

Power grids for sub-micron large integrated circuits are performance limiting factors due to the large power dissipated (e.g. 100 W at 1.8 V). The analysis of such power grids is important in order to predict and possibly improve the performance. Current classical analysis methods are falling behind as grids become ever larger. This paper proposes a new efficient analysis method suitable for both DC and transient simulation of large power grids.

A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a user-supplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value which can be quite tight (under 10% difference between the two in many cases). As a result, the power dissipation is obtained by simulating only a fraction of the potentially very large vector set.